Abstract: A bi-directional full-duplex lock system applied in a data transmission interface of a liquid crystal display is disclosed. The data transmission interface includes a transmitter and a receiver. The bi-directional full-duplex lock system includes a detection module and a control module. The detection module detects a transmitter link state of transmitter and a receiver link state of receiver respectively. The control module controls transmitter to transmit a lock signal to receiver, controls receiver to transmit the lock signal to transmitter, and controls one receiver to transmit the lock signal to another receiver. The lock signal relates to transmitter link state and receiver link state. When transmitter transmits the lock signal to receiver, a phase of the lock signal will be reversed for the receiver to detect whether its own frequency is correct.

Abstract: A voltage mode transmitter includes a resistive network and a de-emphasis value controller. The resistive network receives plural input voltages and provides plural weighting values corresponding to respective input voltages. A sum of the products of the plural input voltages and the corresponding weighting values is equal to an output voltage. The de-emphasis value controller receives a first signal. After the first signal is inverted as an inverted first signal and the inverted first signal is delayed for a time period, the de-emphasis value controller generates a second signal. The de-emphasis value controller further receives a value control signal. At least one of the plural input signals is provided by the first signal and at least one of the plural input signals is provided by the second signal according to the value control signal.

Abstract: A squelch detector receives a first input signal, a second input signal, a first reference voltage and a second reference voltage. The first input signal and the second input signal are collaboratively defined as a differential input signal pair. The difference between the first reference voltage and the second reference voltage is defined as a squelch threshold. According to the squelch threshold, the squelch detector generates a detected signal to indicate whether the differential input signal pair is valid or not.

Abstract: A squelch detector receives a first input signal, a second input signal VM, a first reference voltage and a second reference voltage. The first input signal and the second input signal are collaboratively defined as a differential input signal. The difference between the first reference voltage and the second reference voltage is defined as a squelch threshold. According to the squelch threshold, the squelch detector generates a detected signal to indicate whether the differential input signal is valid.

Abstract: A bi-directional full-duplex lock system applied in a data transmission interface of a liquid crystal display is disclosed. The data transmission interface includes a transmitter and a receiver. The bi-directional full-duplex lock system includes a detection module and a control module. The detection module detects a transmitter link state of transmitter and a receiver link state of receiver respectively. The control module controls transmitter to transmit a lock signal to receiver, controls receiver to transmit the lock signal to transmitter, and controls one receiver to transmit the lock signal to another receiver. The lock signal relates to transmitter link state and receiver link state. When transmitter transmits the lock signal to receiver, a phase of the lock signal will be reversed for the receiver to detect whether its own frequency is correct.

Abstract: A voltage mode transmitter includes a resistive network and a de-emphasis value controller. The resistive network receives plural input voltages and provides plural weighting values corresponding to respective input voltages. A sum of the products of the plural input voltages and the corresponding weighting values is equal to an output voltage. The de-emphasis value controller receives a first signal. After the first signal is inverted as an inverted first signal and the inverted first signal is delayed for a time period, the de-emphasis value controller generates a second signal. The de-emphasis value controller further receives a value control signal. At least one of the plural input signals is provided by the first signal and at least one of the plural input signals is provided by the second signal according to the value control signal.

Abstract: A clock-embedded serial data transmission system is disclosed. The clock-embedded serial data transmission system includes a combinational logic circuit. The combinational logic circuit includes a clock window generator and a clock generator. The clock window generator is used to generate a first clock window according to two clock phases. The clock generator is coupled to a clock window generator and used to select a periodic data within the first clock window from a serial data signal according to the first clock window and generate a recovery clock accordingly.

Abstract: A display includes a panel, a timing controller, and a source driver. A method for driving the display includes the steps of sending a transfer signal asserted for a first period to the source driver initially at a line period; sending a driving control signal asserted for an asserted period to the source driver by the timing controller initially at a line period, utilizing a large driving capability of the source driver to drive the panel during the asserted period within the line period, and utilizing a small driving capability of the source driver to drive the panel beyond the asserted period within the line period.

Abstract: An adaptive equalizer and operating method thereof are disclosed. The adaptive equalizer is oversampling-based. The adaptive equalizer includes a searching module, a compensation module, and an operating module. The searching module searches the equalizer setting from a lower compensation to a higher compensation to obtain a first equalizer setup value according a first monitored result of a monitor and then searches the equalizer setting from a higher compensation to a lower compensation to obtain a second equalizer setup value according to a second monitored result of the monitor. The operating module performs an operation on the first equalizer setup value and the second equalizer setup value to obtain an optimized equalizer setup value.

Abstract: An adaptive equalizer and operating method thereof are disclosed. The adaptive equalizer is oversampling-based. The adaptive equalizer includes a searching module, a compensation module, and an operating module. The searching module searches the equalizer setting from a lower compensation to a higher compensation to obtain a first equalizer setup value according a first monitored result of a monitor and then searches the equalizer setting from a higher compensation to a lower compensation to obtain a second equalizer setup value according to a second monitored result of the monitor. The operating module performs an operation on the first equalizer setup value and the second equalizer setup value to obtain an optimized equalizer setup value.

Abstract: A source driver includes an amplifier, and the amplifier includes an input stage, an output stage, a first current source, a second current source, a third current source, and a switch module. The first current source is utilized to provide a first bias current to the input stage, the second current source is utilized to provide a second bias current to the output stage, and the third current source is utilized to provide a third bias current. The switch module is utilized for selectively connecting the third current source to the input stage or the output stage.

Abstract: A source driver adapted to drive a plurality of data lines on a display panel is disclosed. The source driver includes a first output buffer, a second output buffer, a multiplexer, and a first regulating unit. The first and the second output buffers respectively enhance transmission intensities of a first and a second pixel signals. The first regulating unit regulates a slew rate of the first pixel signal outputted from the first output buffer to match a slew rate of the second pixel signal outputted from the second output buffer. The multiplexer coupled to the regulating unit selectively transmits the first and the second pixel signals to one of the odd data lines and one of the even data line, or to the one of the even data lines or the one of the odd data lines, according to a control signal.

Abstract: A source driver and a driving method thereof are provided. The source driver is adapted to a display panel. The source driver includes an output buffer and a regulating unit. The output buffer has an input terminal and an output terminal. The input terminal of the output buffer receives a pixel signal. The output terminal of the output buffer is coupled to the display panel for outputting an output signal. The regulating unit is coupled to the output terminal of the output buffer, for providing a charging current or a discharging current to the output terminal of the output buffer according to a polarity of the pixel signal. Thereby, a slew rate of the output signal is increased.

Abstract: An output buffer and a source driver using the same are provided. The output buffer includes an input stage module, a first output stage module, a second output stage module, and a first control module. The input stage module generates a first bias signal via a first connection terminal according to a driving signal and a output signal. The first output stage module generates the output signal in response to the first bias signal via an output terminal of the output buffer. The second output stage module generates a second bias signal in response to the first bias signal via a second connection terminal, and controls a first switch in the second output stage module. The first control module selectively connects a first current source to the output terminal of the output buffer or to the second connection terminal of the second output stage module according to an indication signal.

Abstract: A power detecting device, a power supply device using the same, and a reference voltage generator are provided. The power detecting device adapted to detect a power voltage of a display device includes a bandgap voltage generating circuit, a voltage regulating circuit, and a power-on reset circuit. The bandgap voltage generating circuit provides a reference voltage via an output terminal thereof. The voltage regulating circuit and the power-on reset circuit are coupled to the output terminal of the bandgap voltage generating circuit. When the power voltage doesn't reach a threshold voltage, the voltage regulating circuit increases the reference voltage referred by the power-on reset circuit. When the power voltage reaches the reference voltage, the power-on reset circuit generates a reset signal to reset the display device. Therefore, when the power voltage doesn't reach a stable, the power-on reset circuit will not be incorrectly started by increasing the reference voltage.

Abstract: A power detecting device, a power supply device using the same, and a reference voltage generator are provided. The power detecting device adapted to detect a power voltage of a display device includes a bandgap voltage generating circuit, a voltage regulating circuit, and a power-on reset circuit. The bandgap voltage generating circuit provides a reference voltage via an output terminal thereof. The voltage regulating circuit and the power-on reset circuit are coupled to the output terminal of the bandgap voltage generating circuit. When the power voltage doesn't reach a threshold voltage, the voltage regulating circuit increases the reference voltage referred by the power-on reset circuit. When the power voltage reaches the reference voltage, the power-on reset circuit generates a reset signal to reset the display device. Therefore, when the power voltage doesn't reach a stable, the power-on reset circuit will not be incorrectly started by increasing the reference voltage.

Abstract: A source driver adaptive to driving a plurality of data lines on a display panel is provided herein. The source driver includes a plurality of channels and an output switch. The channels generate driving voltages to drive the display panel. The output switch includes a plurality of output multiplexers, so as to selectively connect the channels to data lines of the display. Each of the output multiplexers connects at least one of the channels to one of the data lines while being activated, wherein the output multiplexers are sequentially activated within a frame period. The source driver utilizes the output switch to sequentially delay a control signal, for controlling the output multiplexers to be sequentially activated within the frame period. Therefore, an electromagnetic interference can be reduced for ensuring the source driver operates normally.

Abstract: A source driver includes an amplifier, and the amplifier includes an input stage, an output stage, a first current source, a second current source, a third current source, and a switch module. The first current source is utilized to provide a first bias current to the input stage, the second current source is utilized to provide a second bias current to the output stage, and the third current source is utilized to provide a third bias current. The switch module is utilized for selectively connecting the third current source to the input stage or the output stage.

Abstract: An output buffer and a source driver using the same are provided. The output buffer includes an input stage module, a first output stage module, a second output stage module, and a first control module. The input stage module generates a first bias signal via a first connection terminal according to a driving signal and a output signal. The first output stage module generates the output signal in response to the first bias signal via an output terminal of the output buffer. The second output stage module generates a second bias signal in response to the first bias signal via a second connection terminal, and controls a first switch in the second output stage module. The first control module selectively connects a first current source to the output terminal of the output buffer or to the second connection terminal of the second output stage module according to an indication signal.

Abstract: A source driver and a driving method thereof are provided. The source driver is adapted to a display panel. The source driver includes an output buffer and a regulating unit. The output buffer has an input terminal and an output terminal. The input terminal of the output buffer receives a pixel signal. The output terminal of the output buffer is coupled to the display panel for outputting an output signal. The regulating unit is coupled to the output terminal of the output buffer, for providing a charging current or a discharging current to the output terminal of the output buffer according to a polarity of the pixel signal. Thereby, a slew rate of the output signal is increased.