Abstract: An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.

Abstract: An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.

Abstract: An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.

Abstract: An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.

Abstract: The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same. The nonvolatile memory device comprises: a gate of a stack type structure formed on an active region of a semiconductor substrate; a source/drain formed in the substrate at both sides of the gate of the stack type structure; an interlayer insulating film formed on the substrate where the source/drain is formed and covering the gate of the stack type structure; a contact connected to the source/drain through the interlayer insulating film; a plurality of conductive patterns formed in the interlayer insulating film of the region not adjacent to the contact; and an electrode pad formed on the conductive patterns.

Abstract: The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same. The nonvolatile memory device comprises: a gate of a stack type structure formed on an active region of a semiconductor substrate; a source/drain formed in the substrate at both sides of the gate of the stack type structure; an interlayer insulating film formed on the substrate where the source/drain is formed and covering the gate of the stack type structure; a contact connected to the source/drain through the interlayer insulating film; a plurality of conductive patterns formed in the interlayer insulating film of the region not adjacent to the contact; and an electrode pad formed on the conductive patterns.

Abstract: The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same. The nonvolatile memory device comprises: a gate of a stack type structure formed on an active region of a semiconductor substrate; a source/drain formed in the substrate at both sides of the gate of the stack type structure; an interlayer insulating film formed on the substrate where the source/drain is formed and covering the gate of the stack type structure; a contact connected to the source/drain through the interlayer insulating film; a plurality of conductive patterns formed in the interlayer insulating film of the region not adjacent to the contact; and an electrode pad formed on the conductive patterns.

Abstract: The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same. The nonvolatile memory device comprises: a gate of a stack type structure formed on an active region of a semiconductor substrate; a source/drain formed in the substrate at both sides of the gate of the stack type structure; an interlayer insulating film formed on the substrate where the source/drain is formed and covering the gate of the stack type structure; a contact connected to the source/drain through the interlayer insulating film; a plurality of conductive patterns formed in the interlayer insulating film of the region not adjacent to the contact; and an electrode pad formed on the conductive patterns.

Abstract: The present invention discloses a method for manufacturing a nonvolatile memory transistor capable of minimizing the area when adapted to the technology of sub-micron.

Abstract: The present invention discloses a method for manufacturing a nonvolatile memory transistor capable of minimizing the area when adapted to the technology of sub-micron.