Abstract: An anode active material for a secondary battery includes a carbon-based active material, and silicon-based active material particles doped with magnesium. At least some of the silicon-based active material particles include pores, and a volume ratio of pores having a diameter of 50 nm or less among the pores is 2% or less based on a total volume of the silicon-based active material particles.

Abstract: The technology and implementations disclosed in this patent document generally relate to a lithium secondary battery including: a first unit cell including a first anode including a 1-1 anode mixture layer and a 1-2 anode mixture layer on the 1-1 anode mixture layer, and a second unit cell including a second anode including a 2-1 anode mixture layer and a 2-2 anode mixture layer on the 2-1 anode mixture layer, wherein a weight ratio of the silicon-based active material in the 1-2 anode mixture layer is greater than a weight ratio of the silicon-based active material in the 1-1 anode mixture layer, and a weight ratio of the silicon-based active material in the 2-2 anode mixture layer is less than or equal to a weight ratio of the silicon-based active material in the 2-1 anode mixture layer.

Abstract: An anode for a lithium secondary battery includes an anode current collector, and an anode active material layer formed on at least one surface of the anode current collector. The anode active material layer includes a carbon-based active material, a first silicon-based active material doped with magnesium and a second silicon-based active material not doped with magnesium. A content of the first silicon-based active material is in a range from 2 wt % to 20 wt % based on a total weight of the anode active material layer.

Abstract: In some implementations, the anode includes a current collector, a first anode mixture layer formed on at least one surface of the current collector, and a second anode mixture layer formed on the first anode mixture layer. The first anode mixture layer and the second anode mixture layer include a carbon-based active material, respectively. The first anode mixture layer includes a first binder, a first silicon-based active material, and a first conductive material. The second anode mixture layer includes a second binder, a second silicon-based active material, and a second conductive material. Contents of the first conductive material and the second conductive material are different from each other with respect to the total combined weight of the first anode mixture layer and the second anode mixture layer. Types of the first silicon-based active material and the second silicon-based active material are different from each other.

Abstract: An etching processing apparatus and an etching processing method using a liquid fluorocarbon or a liquid hydrofluorocarbon precursor are proposed, the etching processing apparatus and etching processing method capable of achieving almost the same effect as cryogenic etching even at a relatively high temperature compared to cryogenic etching. In addition, an etching processing apparatus and an etching processing method capable of solving process problems that may arise due to a liquid precursor and a low temperature may be provided.

Abstract: An ion-beam etching apparatus includes: a plasma chamber configured to generate plasma from process gas in the plasma chamber; at least one plasma valve coupled to the plasma chamber; an ion-beam source in communication with the plasma chamber, wherein the ion-beam source is configured to extract ions from the plasma and generate ion-beams when a bias is applied to the ion-beam source; an etching chamber in communication with the ion-beam source, and configured to accommodate an object to be etched; at least one etching valve coupled to the etching chamber; and at least one exhausting pump connected to either one or both of the plasma chamber and the etching chamber by the plasma valve and the etching valve, respectively, wherein the at least one exhausting pump is configured to receive and exhaust radicals in either one or both of the plasma chamber and the etching chamber by the plasma valve and the etching valve, respectively.

Abstract: Disclosed is an inductively-coupled plasma-generating device including: a first power supply for supplying high frequency power; a second power supply for supplying low frequency power; a single coil-based plasma source including at least two antennas which comprise a first antenna having one end as a grounded end and the other end, wherein the first power supply is connected to the first antenna at a point thereof adjacent to the grounded end to receive the high frequency power; and a second antenna surrounded by the first antenna, wherein the second antenna has one end connected to the first antenna and the other end as a low frequency power receiving end connected to the second power supply; and a gas supply for supplying a gas, wherein the gas is excited into plasma by the single coil-based plasma source.

Abstract: Disclosed is an inductively-coupled plasma-generating device including: a first power supply for supplying high frequency power; a second power supply for supplying low frequency power; a single coil-based plasma source including at least two antennas which comprise a first antenna having one end as a grounded end and the other end, wherein the first power supply is connected to the first antenna at a point thereof adjacent to the grounded end to receive the high frequency power; and a second antenna surrounded by the first antenna, wherein the second antenna has one end connected to the first antenna and the other end as a low frequency power receiving end connected to the second power supply; and a gas supply for supplying a gas, wherein the gas is excited into plasma by the single coil-based plasma source.

Abstract: An ion-beam etching apparatus includes: a plasma chamber configured to generate plasma from process gas in the plasma chamber; at least one plasma valve coupled to the plasma chamber; an ion-beam source in communication with the plasma chamber, wherein the ion-beam source is configured to extract ions from the plasma and generate ion-beams when a bias is applied to the ion-beam source; an etching chamber in communication with the ion-beam source, and configured to accommodate an object to be etched; at least one etching valve coupled to the etching chamber; and at least one exhausting pump connected to either one or both of the plasma chamber and the etching chamber by the plasma valve and the etching valve, respectively, wherein the at least one exhausting pump is configured to receive and exhaust radicals in either one or both of the plasma chamber and the etching chamber by the plasma valve and the etching valve, respectively.

Abstract: A non-volatile memory including the following elements is provided. A first conductive layer and a second conductive layer are disposed on a substrate and separated from each other. A patterned hard mask layer is disposed on the first conductive layer and exposes a sharp tip of the first conductive layer. A third conductive layer is disposed on the substrate at one side of the first conductive layer away from the second conductive layer. The third conductive layer is located on a portion of the first conductive layer and covers the sharp tip, and the third conductive layer and the first conductive layer are isolated from each other. A first doped region is disposed in the substrate below the third conductive layer. A second doped region is disposed in the substrate at one side of the second conductive layer away from the first conductive layer.

Abstract: A non-volatile memory including the following elements is provided. A first conductive layer and a second conductive layer are disposed on a substrate and separated from each other. A patterned hard mask layer is disposed on the first conductive layer and exposes a sharp tip of the first conductive layer. A third conductive layer is disposed on the substrate at one side of the first conductive layer away from the second conductive layer. The third conductive layer is located on a portion of the first conductive layer and covers the sharp tip, and the third conductive layer and the first conductive layer are isolated from each other. A first doped region is disposed in the substrate below the third conductive layer. A second doped region is disposed in the substrate at one side of the second conductive layer away from the first conductive layer.

Abstract: A method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory is provided herein. In the method, a bottom silicon oxide layer is formed over a substrate. A patterned mask layer having a trench therein is formed over the bottom silicon oxide layer. A charge-trapping layer is formed over the substrate covering the surface of the trench. The charge-trapping layer is etched back to form a pair of charge storage spacers on the sidewalls of the trench. After removing the mask layer, a top silicon oxide layer is formed over the substrate covering the charge storage spacers and the bottom silicon oxide layer. A gate corresponding to the pair of charge storage spacers is formed on the top silicon oxide layer. A source/drain region is formed in the substrate on each side of the gate.

Abstract: A method of operating a non-volatile memory array is provided. The non-volatile memory array includes a substrate, a number of rows of memory cells, a number of control gate lines, a number of select gate lines, a number of source lines, and a number of drain lines. The operating method includes applying 5V voltage to a selected source line, 1.5V voltage to a selected select gate line, 8V voltage to non-selected select gate lines, 10-12V voltage to a selected control gate line and 0-?2V voltage to non-selected control gate lines and the substrate. The drain lines are grounded so that source-side injection (SSI) is triggered to inject electrons into a floating gate of the selected memory cell in a programming operation.

Abstract: A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region and the drain region are separated from each other by at least two stacked gate structures. A tunneling dielectric layer is formed over the substrate and then a first conductive layer is formed over the tunneling dielectric layer. The first conductive layer is patterned to form floating gates in the gaps between the stacked gate structures. After forming an inter-gate dielectric layer over the substrate, a second conductive layer is formed over the substrate. The second conductive layer is patterned to form mutually linked control gates in the gaps between neighboring stacked gate structures.

Abstract: A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

Abstract: A nonvolatile memory includes a substrate, stacked gate structures, spacers, control gates, a composite dielectric layer and source region/drain regions. Each of stack gate structures is formed on the substrate and is consisted of a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stack gate structure. The composite dielectric layer including a bottom dielectric layer, a charge trapping layer and upper dielectric layer is formed on the substrate. The control gates, which filled in the spaces between the stacked gate structures, are disposed on the composite dielectric layer and connected to each other. The source region/drain region is configured in the substrate near the outer two stacked gate structures.

Abstract: A method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory is provided herein. In the method, a bottom silicon oxide layer is formed over a substrate. A patterned mask layer having a trench therein is formed over the bottom silicon oxide layer. A charge-trapping layer is formed over the substrate covering the surface of the trench. The charge-trapping layer is etched back to form a pair of charge storage spacers on the sidewalls of the trench. After removing the mask layer, a top silicon oxide layer is formed over the substrate covering the charge storage spacers and the bottom silicon oxide layer. A gate corresponding to the pair of charge storage spacers is formed on the top silicon oxide layer. A source/drain region is formed in the substrate on each side of the gate.

Abstract: A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region and the drain region are separated from each other by at least two stacked gate structures. A tunneling dielectric layer is formed over the substrate and then a first conductive layer is formed over the tunneling dielectric layer. The first conductive layer is patterned to form floating gates in the gaps between the stacked gate structures. After forming an inter-gate dielectric layer over the substrate, a second conductive layer is formed over the substrate. The second conductive layer is patterned to form mutually linked control gates in the gaps between neighboring stacked gate structures.

Abstract: A method of manufacturing a non-volatile memory cell is described. The method includes forming a first dielectric layer on a substrate and then forming a patterned mask layer with a trench on the first dielectric layer. A pair of charge storage spacers is formed on the sidewalls of the trench. The patterned mask layer is removed and then a second dielectric is formed on the substrate covering the pair of charge storage spacers. A conductive layer is formed on the second dielectric layer and subsequently patterned to form a gate structure on the pair of charge storage spacers. Portions of the second and first dielectric layers outside the gate structure are removed and then a source/drain region is formed in the substrate on each side of the conductive gate structure.

Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.