Abstract: A non-volatile memory including the following elements is provided. A first conductive layer and a second conductive layer are disposed on a substrate and separated from each other. A patterned hard mask layer is disposed on the first conductive layer and exposes a sharp tip of the first conductive layer. A third conductive layer is disposed on the substrate at one side of the first conductive layer away from the second conductive layer. The third conductive layer is located on a portion of the first conductive layer and covers the sharp tip, and the third conductive layer and the first conductive layer are isolated from each other. A first doped region is disposed in the substrate below the third conductive layer. A second doped region is disposed in the substrate at one side of the second conductive layer away from the first conductive layer.

Abstract: A non-volatile memory including the following elements is provided. A first conductive layer and a second conductive layer are disposed on a substrate and separated from each other. A patterned hard mask layer is disposed on the first conductive layer and exposes a sharp tip of the first conductive layer. A third conductive layer is disposed on the substrate at one side of the first conductive layer away from the second conductive layer. The third conductive layer is located on a portion of the first conductive layer and covers the sharp tip, and the third conductive layer and the first conductive layer are isolated from each other. A first doped region is disposed in the substrate below the third conductive layer. A second doped region is disposed in the substrate at one side of the second conductive layer away from the first conductive layer.

Abstract: A method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory is provided herein. In the method, a bottom silicon oxide layer is formed over a substrate. A patterned mask layer having a trench therein is formed over the bottom silicon oxide layer. A charge-trapping layer is formed over the substrate covering the surface of the trench. The charge-trapping layer is etched back to form a pair of charge storage spacers on the sidewalls of the trench. After removing the mask layer, a top silicon oxide layer is formed over the substrate covering the charge storage spacers and the bottom silicon oxide layer. A gate corresponding to the pair of charge storage spacers is formed on the top silicon oxide layer. A source/drain region is formed in the substrate on each side of the gate.

Abstract: A method of operating a non-volatile memory array is provided. The non-volatile memory array includes a substrate, a number of rows of memory cells, a number of control gate lines, a number of select gate lines, a number of source lines, and a number of drain lines. The operating method includes applying 5V voltage to a selected source line, 1.5V voltage to a selected select gate line, 8V voltage to non-selected select gate lines, 10-12V voltage to a selected control gate line and 0-?2V voltage to non-selected control gate lines and the substrate. The drain lines are grounded so that source-side injection (SSI) is triggered to inject electrons into a floating gate of the selected memory cell in a programming operation.

Abstract: A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region and the drain region are separated from each other by at least two stacked gate structures. A tunneling dielectric layer is formed over the substrate and then a first conductive layer is formed over the tunneling dielectric layer. The first conductive layer is patterned to form floating gates in the gaps between the stacked gate structures. After forming an inter-gate dielectric layer over the substrate, a second conductive layer is formed over the substrate. The second conductive layer is patterned to form mutually linked control gates in the gaps between neighboring stacked gate structures.

Abstract: A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

Abstract: A nonvolatile memory includes a substrate, stacked gate structures, spacers, control gates, a composite dielectric layer and source region/drain regions. Each of stack gate structures is formed on the substrate and is consisted of a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stack gate structure. The composite dielectric layer including a bottom dielectric layer, a charge trapping layer and upper dielectric layer is formed on the substrate. The control gates, which filled in the spaces between the stacked gate structures, are disposed on the composite dielectric layer and connected to each other. The source region/drain region is configured in the substrate near the outer two stacked gate structures.

Abstract: A method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory is provided herein. In the method, a bottom silicon oxide layer is formed over a substrate. A patterned mask layer having a trench therein is formed over the bottom silicon oxide layer. A charge-trapping layer is formed over the substrate covering the surface of the trench. The charge-trapping layer is etched back to form a pair of charge storage spacers on the sidewalls of the trench. After removing the mask layer, a top silicon oxide layer is formed over the substrate covering the charge storage spacers and the bottom silicon oxide layer. A gate corresponding to the pair of charge storage spacers is formed on the top silicon oxide layer. A source/drain region is formed in the substrate on each side of the gate.

Abstract: A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region and the drain region are separated from each other by at least two stacked gate structures. A tunneling dielectric layer is formed over the substrate and then a first conductive layer is formed over the tunneling dielectric layer. The first conductive layer is patterned to form floating gates in the gaps between the stacked gate structures. After forming an inter-gate dielectric layer over the substrate, a second conductive layer is formed over the substrate. The second conductive layer is patterned to form mutually linked control gates in the gaps between neighboring stacked gate structures.

Abstract: A method of manufacturing a non-volatile memory cell is described. The method includes forming a first dielectric layer on a substrate and then forming a patterned mask layer with a trench on the first dielectric layer. A pair of charge storage spacers is formed on the sidewalls of the trench. The patterned mask layer is removed and then a second dielectric is formed on the substrate covering the pair of charge storage spacers. A conductive layer is formed on the second dielectric layer and subsequently patterned to form a gate structure on the pair of charge storage spacers. Portions of the second and first dielectric layers outside the gate structure are removed and then a source/drain region is formed in the substrate on each side of the conductive gate structure.

Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.

Abstract: A non-volatile memory is provided. A plurality of stacked gate structure is formed on the substrate. The stacked gate structure includes, upward from the substrate surface, a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stacked gate structures. The control gates are disposed over the substrate filling the space between the stacked gate structures and are mutually connected together. The floating gates are disposed between the stacked gate structures and positioned between the control gate and the substrate. The inter-gate dielectric layers are disposed between the control gates and the floating gates. The tunneling dielectric layers are disposed between the floating gates and the substrate. The source/drain regions are disposed in the substrate outside the two outermost stacked gate structures.

Abstract: A method of manufacturing a non-volatile memory cell includes forming a first dielectric layer on a substrate. A second dielectric layer having a trench is formed on the first dielectric layer. Thereafter, a pair of charge storage spacers is formed on sidewalls of the trench. A third dielectric layer is then formed over the substrate to cover the first dielectric layer, the charge storage spacers and second dielectric layer. A conductive structure is formed on the third dielectric layer over the charge storage spacers. Subsequently, portions of the third dielectric layer, the second dielectric layer and first dielectric layer not covered by the conductive structure are removed. Ultimately, source/drain regions are formed in the substrate at each side of the conductive structure.

Abstract: A method of forming a gate structure, including forming sequentially a gate dielectric layer, a conductive layer, a protective layer, a sacrificial layer, and a patterned mask layer over a substrate. The exposed sacrificial layer is removed by using the patterned mask layer as an etching mask and the protective layer as an etching stop layer. Spacers are formed on the sidewalls of the sacrificial layer. Subsequently, the exposed protective layer and the conductive layer are removed by using the spacers and the sacrificial layer as etching masks, so as to form gate structures. By forming the protective layer on the conductive layer, the present invention can avoid the top surface of each gate structure from generating sharp corners and also increase the width of each gate structure.

Abstract: A method of forming a flash memory cell. A tunnel oxide layer, a floating gate layer, and a dielectric layer are formed on a substrate. A control gate layer is formed on the dielectric layer and then etched to form two control gates. The control gates are oxidized to form a plurality of second oxide layers on surfaces of the control gates and aside the control gates. The dielectric layer and the floating gate layer are etched by utilizing the second oxide layers as a mask to form a floating gate underneath each of the control gates. A source is formed between the floating gates. The floating gates and the substrate are oxidized to form a plurality of first oxide layers aside the floating gates and form a third oxide layer on a surface of the source.

Abstract: A nonvolatile memory includes a substrate, stacked gate structures, spacers, control gates, a composite dielectric layer and source region/drain regions. Each of stack gate structures is formed on the substrate and is consisted of a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stack gate structure. The composite dielectric layer including a bottom dielectric layer, a charge trapping layer and upper dielectric layer is formed on the substrate. The control gates, which filled in the spaces between the stacked gate structures, are disposed on the composite dielectric layer and connected to each other. The source region/drain region is configured in the substrate near the outer two stacked gate structures.

Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.

Abstract: A non-volatile memory is provided. A plurality of stacked gate structure is formed on the substrate. The stacked gate structure includes, upward from the substrate surface, a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stacked gate structures. The control gates are disposed over the substrate filling the space between the stacked gate structures and are mutually connected together. The floating gates are disposed between the stacked gate structures and positioned between the control gate and the substrate. The inter-gate dielectric layers are disposed between the control gates and the floating gates. The tunneling dielectric layers are disposed between the floating gates and the substrate. The source/drain regions are disposed in the substrate outside the two outermost stacked gate structures.

Abstract: A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

Abstract: A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.