Patents by Inventor Dawei Huang
Dawei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240132492Abstract: The present disclosure provides a class of Pyridopyrimidine compounds having a structure shown in Formula (I) or their pharmaceutically acceptable salts, or stereoisomers or prodrug molecules and applications thereof. The compounds in the present disclosure can efficiently and selectively degrade AKT3 protein in cells without affecting AKT1/2, thereby significantly inhibiting tumor cell proliferation mediated by high expression of AKT3 protein. It can be used to prepare therapeutic drugs for cancer and other diseases related to abnormal expression of AKT3 protein.Type: ApplicationFiled: September 6, 2023Publication date: April 25, 2024Applicants: JINAN UNIVERSITY, SHANGHAI INSTITUTE OF ORGANIC CHEMISTRY, CHINESE ACADEMY OF SCIENCESInventors: Ke DING, Xin ZHANG, Fang XU, Xiaomei REN, Xiaoyun LU, Dawei MA, Weixue HUANG
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Publication number: 20240124486Abstract: A macrocyclic TLR7 agonist, a preparation method therefor, a pharmaceutical composition and use thereof. The macrocyclic TLR7 agonist disclosed is as represented by formula I, has good TLR7 agonistic activity, and can be used for treating or preventing tumors or infections caused by viruses.Type: ApplicationFiled: September 26, 2021Publication date: April 18, 2024Inventors: Guozhi TANG, Dawei MA, Mengwei HUANG, Yongfu LIU, Yingyi WANG
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Publication number: 20240116952Abstract: The disclosure relates to KRASG12D inhibitor compounds having the structure of Formula (A) or Formula (B), pharmaceutical compositions thereof, and methods of use thereof for inhibiting, treating, and/or preventing KRASG12D mutation-associated diseases, disorders and conditions.Type: ApplicationFiled: September 8, 2023Publication date: April 11, 2024Inventors: Jiasheng LU, Xiang JI, Xianchao DU, Yanpeng WU, Xiaolin HE, Guangwei REN, Lina CHU, Chuanhao HUANG, Xingwu ZHU, Yuhua ZHANG, Jian GE, Tianlun ZHOU, Xiangsheng YE, Xianqi KONG, Dawei CHEN
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Patent number: 11886931Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.Type: GrantFiled: November 9, 2021Date of Patent: January 30, 2024Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11886930Abstract: The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.Type: GrantFiled: November 9, 2021Date of Patent: January 30, 2024Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Publication number: 20240020261Abstract: A reconfigurable dataflow unit (RDU) includes an intra-RDU network, an array of configurable units connected by an array level network and function interfaces. The RDU also includes interface circuits coupled between the intra-RDU network and external interconnects. An interface circuit receives a packet from the external interconnect and extracts a target RDU identifier and compares the target RDU identifier to the value of the identity register. It also communicates over the intra-RDU network to a function interface based on information in the first packet in response to the target RDU identifier being equal to the identity register. The interface circuit retrieves another interface circuit identifier for the target RDU identifier from the pass-through table and, in response to the target RDU identifier not being equal to the identity register, sends the target RDU identifier and other information to the other interface circuit over the intra-RDU network.Type: ApplicationFiled: July 5, 2023Publication date: January 18, 2024Applicant: SambaNova Systems, Inc.Inventors: Paul JORDAN, Manish K. SHAH, Emre Ali BURHAN, Dawei HUANG, Yong QIN
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Patent number: 11784855Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.Type: GrantFiled: January 13, 2023Date of Patent: October 10, 2023Assignee: Oracle International CorporationInventors: Xun Zhang, Chaitanya Palusa, Dawei Huang, Muthukumar Vairavan, Jianghui Su
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Publication number: 20230155867Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.Type: ApplicationFiled: January 13, 2023Publication date: May 18, 2023Inventors: Xun Zhang, Chaitanya Palusa, Dawei Huang, Muthukumar Vairavan, Jianghui Su
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Patent number: 11625284Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor on a first node, and a second host processor on a second node. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second host processor using one or more SmartNIC buffers.Type: GrantFiled: November 9, 2021Date of Patent: April 11, 2023Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11625283Abstract: The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.Type: GrantFiled: November 9, 2021Date of Patent: April 11, 2023Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11609798Abstract: The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.Type: GrantFiled: November 9, 2021Date of Patent: March 21, 2023Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Patent number: 11558223Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.Type: GrantFiled: January 25, 2022Date of Patent: January 17, 2023Assignee: Oracle International CorporationInventors: Xun Zhang, Chaitanya Palusa, Dawei Huang, Muthukumar Vairavan, Jianghui Su
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Publication number: 20220197713Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
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Publication number: 20220197709Abstract: The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
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Publication number: 20220197712Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor on a first node, and a second host processor on a second node. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second host processor using one or more SmartNIC buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
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Publication number: 20220197711Abstract: The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
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Publication number: 20220197710Abstract: The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.Type: ApplicationFiled: November 9, 2021Publication date: June 23, 2022Applicant: SambaNova Systems, Inc.Inventors: Ram SIVARAMAKRISHNAN, Sumti JAIRATH, Emre Ali BURHAN, Manish K. SHAH, Raghu PRABHAKAR, Ravinder KUMAR, Arnav GOEL, Ranen CHATTERJEE, Gregory Frederick GROHOSKI, Kin Hing LEUNG, Dawei HUANG, Manoj UNNIKRISHNAN, Martin Russell RAUMANN, Bandish B. SHAH
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Publication number: 20220191071Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.Type: ApplicationFiled: January 25, 2022Publication date: June 16, 2022Inventors: Xun Zhang, Chaitanya Palusa, Dawei Huang, Muthukumar Vairavan, Jianghui Su
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Patent number: 11240073Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.Type: GrantFiled: October 31, 2019Date of Patent: February 1, 2022Assignee: Oracle International CorporationInventors: Xun Zhang, Chaitanya Palusa, Dawei Huang, Muthukumar Vairavan, Jianghui Su
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Patent number: 11182264Abstract: A data processing system comprises a plurality of reconfigurable processors including a first reconfigurable processor and additional reconfigurable processors, a plurality of buffers in a shared memory accessible to the first reconfigurable processor and the additional reconfigurable processors, and runtime logic configured to execute one or more configuration files for applications using the first reconfigurable processor and the additional reconfigurable processors. Execution of the configuration files includes receiving data from the first reconfigurable processor and providing the data to at least one of the additional reconfigurable processors, and receiving data from the at least one of the additional reconfigurable processors and providing the data to the first reconfigurable processor.Type: GrantFiled: December 18, 2020Date of Patent: November 23, 2021Assignee: SambaNova Systems, Inc.Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah