Abstract: A wheel for reducing a resonance noise in a vehicle may include a cylindrical-shaped rim on which a tire is mounted, and waveguides mounted on the rim, disposed in a cavity which is a space between the rim and the tire, having a ‘U’-shaped internal passage through which a sound wave generated in the cavity enters, and configured to reflect the sound wave entering the internal passage to generate a sound wave having an inverse phase, wherein a center portion of the internal passage extends in an axial direction of the rim, and first and second end portions of the internal passage are connected to a center portion of the internal passage to allow the sound wave to propagate and extend in a circumferential direction of the rim.

Abstract: An integrated circuit layout includes: a first chip area; and a second chip area, wherein the first chip area includes: a first main area including a first main pattern; a first mark area adjacent to the first main area, wherein a first mark pattern is formed in the first mark area; and a first dummy area including a first dummy pattern, wherein the second chip area includes: a second main area including a second main pattern; a second mark area adjacent to the second main area, wherein a second mark pattern is formed in the second mark area; and a second dummy area including a second dummy pattern, wherein the first and second mark patterns are used to check alignment states of the first chip area and the second chip area, respectively, and wherein each of the first and second mark patterns has a standard cell structure.

Abstract: A semiconductor device includes a substrate, a first active pattern extending in a first horizontal direction, a second active pattern extending in the first horizontal direction and spaced apart from the first active pattern in a second horizontal direction, a gate electrode extending in the second horizontal direction, a source/drain region disposed on a side of the gate electrode, a first through-via disposed inside the substrate between the first and second active patterns, an upper interlayer insulating layer covering the source/drain region, and a second through-via connected to the first through-via by passing through the upper interlayer insulating layer in a vertical direction spaced apart from the source/drain region in the second horizontal direction. A width of the first through-via in the second horizontal direction is continuously reduced as the first through-via becomes adjacent to the lower surface of the substrate.

Abstract: An optical proximity correction (OPC) whereby corner rounding may be effectively controlled, and a mask manufacturing method performed using the OPC method are provided. According to the OPC method, an inner edge is generated through decomposition of a layout, and a displacement (DISin_frag) of an inner fragment and a displacement (DISsel) of a selected fragment are calculated based on the inner edge to additionally displace a fragment, so as to manufacture a mask layout with minimized corner rounding without violating mask rule check (MRC).

Abstract: An optical proximity correction (OPC) whereby corner rounding may be effectively controlled, and a mask manufacturing method performed using the OPC method are provided. According to the OPC method, an inner edge is generated through decomposition of a layout, and a displacement (DISin_frag) of an inner fragment and a displacement (DISsel) of a selected fragment are calculated based on the inner edge to additionally displace a fragment, so as to manufacture a mask layout with minimized corner rounding without violating mask rule check (MRC).