Abstract: Methods and systems for adjusting phase lock loop devices. In a specific embodiment, the subject technology provides a system that includes a sampler for generating samples from a first data stream and a clock and data recovery (CDR) circuit to determine phase offset and generate a first control code. The system also includes a phase interpolator produces a first clock signal based on the first control code and a second clock signal. The system includes a first filter configured to track the phase interpolator movement, and it generates a second control code that includes a fractional divider value. The system includes a phase-locked loop (PLL) circuit that uses a reference clock to generate the second clock signal based on the third clock signal and the second control code. There are other embodiments as well.

Abstract: A system for controlling jitter includes a first phase interpolator, a second phase interpolator, a first circuit configured to receive a first signal provided to the first phase interpolator, a second circuit configured to receive a second signal provided to the second phase interpolator, and a third circuit configured to provide a phase control signal in response to the first signal and the second signal. The first signal represents a first phase adjustment, and the second signal represents a second phase adjustment.

Abstract: A system for controlling jitter includes a first phase interpolator, a second phase interpolator, a first circuit configured to receive a first signal provided to the first phase interpolator, a second circuit configured to receive a second signal provided to the second phase interpolator, and a third circuit configured to provide a phase control signal in response to the first signal and the second signal. The first signal represents a first phase adjustment, and the second signal represents a second phase adjustment.