Patents by Inventor Da-Yuan Lee

Da-Yuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190273145
    Abstract: Certain embodiments of a semiconductor device and a method of forming a semiconductor device comprise forming a high-k gate dielectric layer over a short channel semiconductor fin. A work function metal layer is formed over the high-k gate dielectric layer. A seamless metal fill layer is conformally formed over the work function metal layer.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Hang CHIU, Chung-Chiang WU, Ching-Hwanq SU, Da-Yuan LEE, Ji-Cheng CHEN, Kuan-Ting LIU, Tai-Wei HWANG, Chung-Yi SU
  • Publication number: 20190259861
    Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).
    Type: Application
    Filed: April 29, 2019
    Publication date: August 22, 2019
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Ching-Hwanq Su
  • Publication number: 20190259753
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
  • Publication number: 20190259853
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Hsueh Wen Tsau
  • Publication number: 20190245053
    Abstract: A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 8, 2019
    Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 10312236
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
  • Patent number: 10304835
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Patent number: 10297453
    Abstract: Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A second metal-containing layer is formed on the substrate. A material of the first metal-containing layer is different from a material of the second metal-containing layer. A chlorine-based treatment is performed on the first metal-containing layer and the second metal-containing layer. A third metal-containing layer is deposited on the first metal-containing layer and the second metal-containing layer using Atomic Layer Deposition (ALD).
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Da-Yuan Lee, JoJo Lee, Ming-Hsing Tsai, Hsueh Wen Tsau, Weng Chang, Ying-Chieh Hung, Yi-Hung Lin
  • Patent number: 10283619
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Hsueh Wen Tsau
  • Patent number: 10276690
    Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 10269912
    Abstract: A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 10256311
    Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a first gate having top and bottom portions of different widths, the top portion of the first gate being disposed above the bottom portion of the first gate. The FinFET also includes a second gate having top and bottom portions of different widths, the top portion of the second gate being disposed above the bottom portion of the second gate. A first inter-layer dielectric layer is disposed between the first gate and the second gate in an interposed manner. The first inter-layer dielectric layer has a thickness equal to a height of the bottom portions of the first and second gates. A second inter-layer dielectric layer is patterned over the first inter-layer dielectric layer.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsueh-Wen Tsau, Chia-Ching Lee, Mrunal A. Khaderbad, Da-Yuan Lee
  • Publication number: 20190067279
    Abstract: A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the polysilicon gate structure with a metal gate structure. Replacing the polysilicon gate structure includes depositing a work function metal layer over the plurality of fins, forming a metal oxide layer over the work function metal layer, and depositing a first metal layer over the metal oxide layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of fins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh Wen TSAU, Chia-Ching LEE, Chung-Chiang WU, Da-Yuan LEE
  • Publication number: 20190035916
    Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).
    Type: Application
    Filed: September 14, 2017
    Publication date: January 31, 2019
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 10170417
    Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.
    Type: Grant
    Filed: November 19, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Hsueh-Wen Tsau, Chun-Yuan Chou, Cheng-Yen Tsai, Da-Yuan Lee, Ming-Hsing Tsai
  • Patent number: 10157998
    Abstract: A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Da-Yuan Lee, Hsin-Yi Lee, Kuan-Ting Liu
  • Patent number: 10128237
    Abstract: A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the polysilicon gate structure with a metal gate structure. Replacing the polysilicon gate structure includes depositing a work function metal layer over the plurality of fins, forming a metal oxide layer over the work function metal layer, and depositing a first metal layer over the metal oxide layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of fins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh Wen Tsau, Chia-Ching Lee, Chung-Chiang Wu, Da-Yuan Lee
  • Publication number: 20180308944
    Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventors: Mrunal A. KHADERBAD, Hsueh Wen TSAU, Chia-Ching LEE, Da-Yuan LEE, Hsiao-Kuan WEI, Chih-Chang HUNG, Huicheng CHANG, Weng CHANG
  • Patent number: 10096600
    Abstract: A semiconductor device including a first gate structure is disposed on the semiconductor substrate. The first gate structure includes a gate dielectric layer, a layer, a first work function metal, a second work function metal, and a fill metal. A second gate structure is also disposed on the semiconductor substrate. The second gate structure includes the gate dielectric layer, a second work function metal, and the fill metal. In an embodiment, the second gate structure also includes an etch stop layer.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Da-Yuan Lee, Kuang-Yuan Hsu
  • Publication number: 20180261459
    Abstract: A system for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.
    Type: Application
    Filed: May 15, 2018
    Publication date: September 13, 2018
    Inventors: Cheng-Yen TSAI, Hsin-Yi LEE, Chung-Chiang WU, Da-Yuan LEE, Weng CHANG, Ming-Hsing TSAI