Abstract: This invention provides a capacitor structure includes a U-shaped bottom electrode having a cap dielectric provided at its open end, a top electrode and a capacitor dielectric layer interposed between the bottom electrode and the top electrode to constitute an outer capacitor around a cylinder type solid inner capacitor, and the outer capacitor and the inner capacitor are divided by the cap dielectric. The cylinder type solid inner capacitor and the outer capacitor are fabricated separately so that the cylinder type solid inner capacitor may support its own weight to prevent its structure from being damaged during the fabrication of the capacitor.

Abstract: A method for forming a shallow trench isolation (STI) structure using two individual STI trench etching processes is provided. A first STI etching process forms first trenches with one or more sizes in rows along a first dimension in a silicon substrate. A first dielectric is filled in the first trenches following a first thermal oxidation forming a first liner oxide surrounding the first trenches. A second STI trench etching process forms second trenches with one or more sizes in a second dimension to define active regions separated from each other by the first trenches filled with the first dielectric material and second trenches. A second dielectric is filled in the second trenches following a second thermal oxidation forming a second liner oxide surrounding the second trenches. Active region encroachment caused by the first and second thermal oxidation is reduced by doing the two individual STI trench etching processes.

Abstract: A method for forming a shallow trench isolation (STI) structure using two individual STI trench etching processes is provided. A first STI etching process forms first trenches with one or more sizes in rows along a first dimension in a silicon substrate. A first dielectric is filled in the first trenches following a first thermal oxidation forming a first liner oxide surrounding the first trenches. A second STI trench etching process forms second trenches with one or more sizes in a second dimension to define active regions separated from each other by the first trenches filled with the first dielectric material and second trenches. A second dielectric is filled in the second trenches following a second thermal oxidation forming a second liner oxide surrounding the second trenches. Active region encroachment caused by the first and second thermal oxidation is reduced by doing the two individual STI trench etching processes.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate comprising a memory region and a logic region; forming a memory gate in or on the memory region; forming a plurality of first poly-silicon gates on the memory region and surrounding the memory gate; and forming a plurality of second poly-silicon gates on the logic region simultaneously with the formation of the first poly-silicon gates.

Abstract: A method for forming a shallow trench isolation (STI) structure using two individual STI trench etching processes is provided. A first STI etching process forms first trenches with one or more sizes in rows along a first dimension in a silicon substrate. A first dielectric is filled in the first trenches following a first thermal oxidation forming a first liner oxide surrounding the first trenches. A second STI trench etching process forms second trenches with one or more sizes in a second dimension to define active regions separated from each other by the first trenches filled with the first dielectric material and second trenches. A second dielectric is filled in the second trenches following a second thermal oxidation forming a second liner oxide surrounding the second trenches. Active region encroachment caused by the first and second thermal oxidation is reduced by doing the two individual STI trench etching processes.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate comprising a memory region and a logic region; forming a memory gate in or on the memory region; forming a plurality of first poly-silicon gates on the memory region and surrounding the memory gate; and forming a plurality of second poly-silicon gates on the logic region simultaneously with the formation of the first poly-silicon gates.

Abstract: The present disclosure provides a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a memory cell, a first logic transistor, and a second logic transistor. The semiconductor substrate includes a memory region and a logic region. The memory cell is disposed in the memory region. The first logic transistor is disposed in the memory region and disposed adjacent to the memory cell. The second logic transistor is disposed in the logic region. The first logic transistor is configured to control operation of the memory cell in response to a memory control signal provided by the second logic transistor.

Abstract: The present disclosure provides a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a memory cell, a first logic transistor, and a second logic transistor. The semiconductor substrate includes a memory region and a logic region. The memory cell is disposed in the memory region. The first logic transistor is disposed in the memory region and disposed adjacent to the memory cell. The second logic transistor is disposed in the logic region. The first logic transistor is configured to control operation of the memory cell in response to a memory control signal provided by the second logic transistor.

Abstract: The present disclosure provides a DRAM cell structure. The DRAM cell structure includes a substrate, a gate structure disposed in the substrate, a source region and a drain region disposed in the substrate respectively at two sides of the gate structure, a landing pad disposed over the drain region, a plurality of carbon nanotubes disposed on the landing pad, a top electrode disposed over the plurality of carbon nanotubes, and a dielectric layer disposed between the top electrode and the plurality of carbon nanotubes.

Abstract: The present disclosure provides a DRAM cell structure. The DRAM cell structure includes a substrate, a gate structure disposed in the substrate, a source region and a drain region disposed in the substrate respectively at two sides of the gate structure, a landing pad disposed over the drain region, a plurality of carbon nanotubes disposed on the landing pad, a top electrode disposed over the plurality of carbon nanotubes, and a dielectric layer disposed between the top electrode and the plurality of carbon nanotubes.

Abstract: The present disclosure provides a DRAM cell structure. The DRAM cell structure includes a substrate, a gate structure disposed in the substrate, a first source/drain region and a second source/drain region disposed in the substrate respectively at two sides of the gate structure, a landing pad disposed over the second source/drain region, a plurality of conductive pillars disposed on the landing pad, a conductive layer disposed over the plurality of conductive pillars, and a dielectric layer disposed between the conductive layer and the plurality of conductive pillars. The plurality of conductive pillars have at least a first width and a second width, and the first width and the second width are different from each other.

Abstract: An electronic apparatus comprising a unified non-volatile memory and a control unit is disclosed. The unified non-volatile memory comprises a first memory section, served as a read only memory; and a second memory section, served as a random access memory. The control unit controls the unified non-volatile memory. The first memory section further comprises: a first area for the first memory section; and a second area for the first memory section. The control unit adjusts a refresh rate of the second memory section according to a number of access times of the second memory section.

Abstract: An electronic apparatus comprising a unified non-volatile memory and a control unit is disclosed. The unified non-volatile memory comprises a first memory section, served as a read only memory; and a second memory section, served as a random access memory. The control unit controls the unified non-volatile memory. The first memory section further comprises: a first area for the first memory section; and a second area for the first memory section. The control unit adjusts a refresh rate of the second memory section according to an amount of access times of the second memory section.

Abstract: Discloses is a unified non-volatile memory comprising: a first memory section, served as a read only memory; and a second memory section, served as a random access memory. An electronic apparatus applying the unified non-volatile memory is also disclosed.

Abstract: The invention relates to a semiconductor process, and in particular to a method and structure of manufacturing contact windows between different levels of two conductive layers (a upper conductive layer and a lower conductive layer) in the semiconductor process. In the method, first, a trench is formed under a subsequently-formed contact window between the upper conductive layer and lower conductive layer. The trench may be located on the insulating layer under the lower conductive layer. When the lower conductive layer is subsequently formed, the trench can be filled with the lower conductive layer. Therefore, part of the lower conductive layer on the trench is thicker than that on the other regions. When the insulating layer between the upper conductive layer and lower conductive layer is formed, an etching process is then performed to form the contact window, the contact window can not cross the lower conductive layer due to the lower conductive layer on the trench being sufficiently thick.

Abstract: The invention relates to a semiconductor process, and in particular to a method and structure of manufacturing contact windows between different levels of two conductive layers (a upper conductive layer and a lower conductive layer) in the semiconductor process. In the method, first, a trench is formed under a subsequently-formed contact window between the upper conductive layer and lower conductive layer. The trench may be located on the insulating layer under the lower conductive layer. When the lower conductive layer is subsequently formed, the trench can be filled with the lower conductive layer. Therefore, part of the lower conductive layer on the trench is thicker than that on the other regions. When the insulating layer between the upper conductive layer and lower conductive layer is formed, an etching process is then performed to form the contact window, the contact window can not cross the lower conductive layer due to the lower conductive layer on the trench being sufficiently thick.

Abstract: A method is disclosed to manufacture a capacitor structure having a high capacitance and a flat topography on a semiconductor device. The method includes steps of: (a) forming a first insulating layer over a substrate having a transistor structure; (b) forming a first and a second contact holes on the first insulating layer; (c) forming a first conducting layer over the first insulating layer; (d) forming a bit line structure above the first contact hole; (e) forming an etching stop layer and a second insulating layer over the substrate, and removing a portion of the etching stop layer and the second insulating layer for forming a capacitor area wherein the second contact plug is exposed; (f) forming a second conducting layer over the substrate, and forming a sacrificial layer in the capacitor area for covering a portion of the second conducting layer; (g) forming the capacitor structure in the capacitor area.

Abstract: A modified LOCOS isolation process for semiconductor devices is disclosed. First, a shielding layer is formed overlying a semiconductor substrate. The shielding layer is then patterned to form an opening that exposes a portion of the semiconductor substrate for forming a device isolation region. Next, oxygen ions are implanted with a tilt angle into the semiconductor substrate to form a doped region extending to the area under the margin of the shielding layer. A thermal oxidation process is then performed to form a field oxide layer on the semiconductor substrate. Since the oxidation rate of the area under the margin of the shielding layer is increased by the implanted oxygen ions, the bird's beak effect shown in conventional LOCOS process can be eliminated. After that, the shielding layer is removed to complete the fabricating process of this invention.