Abstract: A display substrate including a drive-circuit layer and a light-emitting structure layer, a preparation method thereof, and a display device, the light-emitting structure layer includes an anode, a pixel definition layer, an organic light-emitting layer and a cathode, and an auxiliary electrode and an organic light-emitting block, arranged sequentially, the pixel definition layer includes an anode opening exposing the anode and an electrode opening exposing the auxiliary electrode, the organic light-emitting block is separated from the organic light-emitting layer, the auxiliary electrode includes the first, second and third auxiliary electrodes arranged sequentially; the cathode includes a first horizontal lapping part lapping with the first auxiliary electrode and a second sidewall lapping part lapping with the second auxiliary electrode, the thickness of the second sidewall lapping part in the direction parallel to the substrate is greater than that of the first horizontal lapping part in the direction per

Abstract: A meeting managing method, a server and a meeting managing system, and relates to the technical field of computers. The method according to the present application includes receiving data of a plurality of participants sent by a first client; binding data of each participant in the plurality of participants with a corresponding electronic-table-card identifier, wherein electronic table cards corresponding to each of the electronic-table-card identifiers correspond to microphones one to one; receiving the voice data sent by the target microphone; according to a target-electronic-table-card identifier corresponding to the target microphone, determining data of the target participant; and according to the voice data and the data of the target participant, generating a meeting document.

Abstract: A conference system is provided, including: a server, wherein the server is configured to reserve a conference room according to a conference application information received, wherein the conference application information includes an information of a target conference room; and wherein the server is further configured to determine a conference terminal device associated with the target conference room and push a conference information associated with the conference application information to the conference terminal device to display the conference information. A method and a device of pushing conference information are also provided.

Abstract: Disclosed a screw tightening angle conversion head, including a conversion head body, wherein one end of which is fixedly provided with a mounting groove, a fixed cover plate is fixedly arranged at the upper end of the mounting groove, a transmission worm is rotatably arranged at one end inside the conversion head body close to the mounting groove, one end of the transmission worm penetrates through the conversion head body and extends out from an outer end, a rotating seat is fixedly arranged at a rotational junction between the transmission worm and the inside of the conversion head body, annular worm teeth are fixedly arranged at the outer side of the transmission worm, a rotating shaft is rotatably arranged at one end inside the conversion head body away from the transmission worm, and the outer wall of the rotating shaft is fixedly connected with an intermediate gear.

Abstract: Systems and methods are provided for a pipelined analog-to-digital converter (ADC) circuit. The pipelined ADC circuit comprises a plurality of stages. Each stage comprises a differential input configured to receive a differential signal, a multiplying digital-to-analog converter (MDAC) electrically coupled to the input configured to stack voltages of a set of capacitors; a comparator electrically disposed after the MDAC to compare the differential voltages; and a source follower buffer electrically coupled to the first signal line and the second signal line and electrically disposed after the comparator, wherein the MDAC is configured to amplify an output voltage using passive multiplication; and an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages, wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal.

Abstract: Systems and methods are provided for a pipelined analog-to-digital converter (ADC) circuit. The pipelined ADC circuit comprises a plurality of stages. Each stage comprises a differential input configured to receive a differential signal, a multiplying digital-to-analog converter (MDAC) electrically coupled to the input configured to stack voltages of a set of capacitors; a comparator electrically disposed after the MDAC to compare the differential voltages; and a source follower buffer electrically coupled to the first signal line and the second signal line and electrically disposed after the comparator, wherein the MDAC is configured to amplify an output voltage using passive multiplication; and an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages, wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal.

Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

Abstract: One embodiment can provide a sampler for a decision feedback equalizer (DFE). The sampler can include a comparator comprising a resolver and a plurality of amplifiers coupled to the resolver. The plurality of amplifiers are to receive an input signal and one or more feedback signals, and the plurality of amplifiers are coupled to each other in parallel, thereby facilitating a summation of the input signal and the one or more feedback signals. The comparator is to generate an output based on the summation of the input signals and the one or more feedback signals. The sampler can further include an inverter to invert the output of the comparator. The inverted output of the inverter is sent to a tap-1 amplifier to generate a tap-1 feedback signal to be sent to the comparator at a next unit interval (UI).

Abstract: Apparatus, methods and systems to produce a protection voltage are disclosed. The apparatus includes circuitry to deliver a first supply voltage to a plurality of circuits, where the first supply voltage has a first magnitude, circuitry to deliver a second supply voltage to a part of the plurality of circuits, where the second supply voltage has a second magnitude, and circuitry to deliver a protection voltage to the part of the plurality of circuits when the second supply voltage is LOW and the first supply voltage is HIGH. The protection voltage has a magnitude that is a fraction of the magnitude of the first supply voltage. The apparatus includes circuitry that causes the delivery of the second supply voltage to the part of the plurality of circuits when the second supply voltage is turned HIGH subsequent to the second supply voltage being LOW when the first supply voltage is HIGH.

Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.

Abstract: A technique includes determining a first phase delay associated with communication of a bit pattern having a first bit transition frequency over a communication channel; and determining a second phase delay associated with communication of a bit pattern having a second bit transition frequency greater than the first bit transition frequency over the communication channel. The technique includes regulating a compensation applied to a signal received from the communication channel based at least in part on a difference of the first and second phase delays.

Abstract: Apparatus, methods and systems to produce a protection voltage are disclosed. The apparatus includes circuitry to deliver a first supply voltage to a plurality of circuits, where the first supply voltage has a first magnitude, circuitry to deliver a second supply voltage to a part of the plurality of circuits, where the second supply voltage has a second magnitude, and circuitry to deliver a protection voltage to the part of the plurality of circuits when the second supply voltage is LOW and the first supply voltage is HIGH. The protection voltage has a magnitude that is a fraction of the magnitude of the first supply voltage. The apparatus includes circuitry that causes the delivery of the second supply voltage to the part of the plurality of circuits when the second supply voltage is turned HIGH subsequent to the second supply voltage being LOW when the first supply voltage is HIGH.

Abstract: A differential amplifier includes a pair of cascode amplifiers. A voltage clamp is coupled to the pair of cascode amplifiers.

Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.

Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

Abstract: A technique includes determining a first phase delay associated with communication of a bit pattern having a first bit transition frequency over a communication channel; and determining a second phase delay associated with communication of a bit pattern having a second bit transition frequency greater than the first bit transition frequency over the communication channel. The technique includes regulating a compensation applied to a signal received from the communication channel based at least in part on a difference of the first and second phase delays.

Abstract: An example driver circuit includes a termination voltage circuit and a termination element coupled to the termination voltage circuit. The driver circuit also includes a current source switch coupled the termination element via a node. The driver circuit further includes a current source coupled to the current source switch. The current source switch and the termination voltage circuit are controlled via a control signal. The termination voltage circuit is to generate a termination voltage to match a node voltage of the node based on the control signal. The driver circuit further includes a load coupled to the termination element and the current source switch via the node. The driver circuit further includes a load voltage source coupled to the load. The node voltage is generated based on the load and the load voltage source.

Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

Abstract: A differential amplifier includes a pair of cascode amplifiers. A voltage clamp is coupled to the pair of cascode amplifiers.

Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.