Abstract: A testing device includes a connecting module and a processor electrically connected to the connecting module. The connecting module is electrically coupled with a plurality of communication devices under tests (DUTs) synchronously. The processor determines a schedule for the communication DUTs and tests the communication DUTs according to the schedule. A testing method is applied to the testing device to implement the operations.

Abstract: A testing device of a signaling mode and a testing method thereof are provided. The testing device includes a connecting module and a processor electrically connected to the connecting module. The connecting module is configured to electrically couple with a plurality of communication devices under tests (DUTs) simultaneously. The processor is configured to execute a network attaching procedure between the testing device and each of the communication DUTs, wherein the network attaching procedures are overlapped to be executed. The processor is further configured to test the communication DUTs after executing the network attaching procedures.

Abstract: A testing device and a testing method are provided. The testing device includes a connecting module and a processor electrically connected to the connecting module. The connecting module is electrically coupled with a plurality of communication devices under tests (DUTs) synchronously. The processor determines a schedule for the communication DUTs and tests the communication DUTs according to the schedule. The testing method is applied to the testing device to implement the aforesaid operations.

Abstract: An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of chiprate (S)(n) in a primary mode, and a secondiary digital transceiver clock signal having a frequency of chiprate in a secondary power saving mode. A chiprate divider connected to the output of the clock generator produces a primary mode enable signal that has a frequency of chiprate when in a primary mode. A long PN generator and a short PN generator each have a clock input that is coupled to the output of the clock generator. A first multiplexer output produces the primary mode enable signal in a primary mode, and the secondary mode enable signal in a secondary mode.

Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate(S).

Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S).