Abstract: A NAND-type nonvolatile semiconductor memory device comprising a cell string that comprises a dummy cell interposed between and connected in series to a string selection transistor and a nonvolatile memory cell is provided. The NAND-type nonvolatile semiconductor memory device further comprises a dummy word line driver adapted to activate a dummy word line to gate the dummy cell.

Abstract: In one aspect, a programming method is provided for a non-volatile semiconductor memory device which includes a plurality of electrically programmable and erasable memory cells, and transmission transistors for providing predetermined voltages to the memory cells. The method includes a primary programming process which includes providing a first program voltage to a selected memory cell to program the selected memory cell, a verify read process which includes reading the selected memory cell to verify a programmed status of the selected memory cell resulting from the primary programming process, and a secondary programming process which includes providing a second program voltage to the selected memory cell so as to reprogram the selected memory cell after the verify read process. During the verify read process, the transmission transistors are continuously gated by a boosted voltage generated during the primary programming process.

Abstract: An integrated circuit memory device includes a memory cell array including first and second bit lines that extend side-by-side, a plurality of page buffers, a first isolation device electrically coupled to an end of the first bit line, and a second isolation device electrically coupled to an end of the second bit line. The second isolation device is arranged farther from the plurality of page buffers than the first isolation device. A first connection line is electrically coupled at a first end thereof to the first isolation device, and is electrically coupled at a second end thereof to one of the plurality of page buffers. A second connection line is electrically coupled at a first end thereof to the second isolation device, and is electrically coupled at a second end thereof to a farther one of the plurality of page buffers. The second connection line is arranged immediately adjacent to the first bit line.