Patents by Inventor Dae Byoung Kang

Dae Byoung Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10242956
    Abstract: A semiconductor device is disclosed that may include a first semiconductor die comprising a copper pillar, a second semiconductor die comprising a copper pillar, and a conductive bump connecting the copper pillar of the first semiconductor die to the copper pillar of the second semiconductor die. The first semiconductor die may comprise a metal dam formed between the copper pillar and a bond pad on the first semiconductor die. The conductive bump may have a melting point lower than melting points of the copper pillar of the first semiconductor die and the copper pillar of the second semiconductor die. The first semiconductor die may be coupled to a substrate with a conductive wire coupled to the bond pad and to the substrate. The first semiconductor die may comprise a redistribution layer formed beneath the copper pillar on the first semiconductor die.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 26, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Dong Hee Lee, Min Yoo, Dae Byoung Kang, Bae Yong Kim
  • Publication number: 20180308788
    Abstract: In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body.
    Type: Application
    Filed: July 2, 2018
    Publication date: October 25, 2018
    Applicant: AMKOR TECHNOLOGY, INC.
    Inventors: Dong Joo PARK, Jin Seong KIM, Ki Wook LEE, Dae Byoung KANG, Ho CHOI, Kwang Ho KIM, Jae Dong KIM, Yeon Soo JUNG, Sung Hwan CHO
  • Patent number: 10037949
    Abstract: A semiconductor package that includes EMI shielding and a fabricating method thereof are disclosed. In one embodiment, the fabricating method of a semiconductor package includes forming a substrate, attaching semiconductor devices to a top portion of the substrate, encapsulating the semiconductor devices using an encapsulant, forming a trench in the encapsulant, and forming a shielding layer on a surface of the encapsulant.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: July 31, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Hee Sung Kim, Yeoung Beom Ko, Dae Byoung Kang, Jae Jin Lee, Joon Dong Kim, Dong Jean Kim
  • Publication number: 20180096928
    Abstract: A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 5, 2018
    Inventors: Keun Soo Kim, Jae Yun Kim, Byoung Jun Ahn, Dong Soo Ryu, Dae Byoung Kang, Chel Woo Park
  • Patent number: 9859203
    Abstract: A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 2, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Keun Soo Kim, Jae Yun Kim, Byoung Jun Ahn, Dong Soo Ryu, Dae Byoung Kang, Chel Woo Park
  • Publication number: 20170117214
    Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body.
    Type: Application
    Filed: December 26, 2016
    Publication date: April 27, 2017
    Applicant: AMKOR TECHNOLOGY, INC.
    Inventors: Dong Joo PARK, Jin Seong KIM, Ki Wook LEE, Dae Byoung KANG, Ho CHOI, Kwang Ho KIM, Jae Dong KIM, Yeon Soo JUNG, Sung Hwan CHO
  • Publication number: 20160225692
    Abstract: A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 4, 2016
    Inventors: Keun Soo Kim, Jae Yun Kim, Byoung Jun Ahn, Dong Soo Ryu, Dae Byoung Kang, Chel Woo Park
  • Publication number: 20150303170
    Abstract: A singulated substrate for a semiconductor device may include a singulated unit substrate comprising circuit patterns on a top surface and a bottom surface of the singulated unit substrate. A semiconductor die may be bonded to the top surface of the singulated unit substrate. An encapsulation layer may encapsulate the semiconductor die and cover the top surface of the singulated unit substrate. The side surfaces of the singulated unit substrate between the top surface and bottom surface of the singulated unit substrate may be coplanar with side surfaces of the encapsulation layer. The semiconductor die may be electrically coupled to the singulated unit substrate utilizing solder bumps. Solder balls may be formed on the circuit patterns on the bottom surface of the singulated unit substrate. An underfill material may be formed between the semiconductor die and the top surface of the singulated unit substrate.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 22, 2015
    Applicant: Amkor Technology, Inc.
    Inventors: Keun Soo Kim, Byoung Jun Ahn, Choon Heung Lee, Jin Young Kim, Dae Byoung Kang, Roger St. Amand
  • Patent number: 8890329
    Abstract: A semiconductor device entirely having a small height, which performs a fan-out operation for input/output signals and forms a short electrical path is provided. The semiconductor device includes a first semiconductor die having a first surface, a second surface opposed to the first surface, a third surface connecting the first and second surfaces to each other, a first bond pad disposed on the first surface, and a first through electrode passing between the first surface and second surface and electrically connected to the first bond pad. A first redistribution part is disposed under the second surface and includes a first redistribution layer electrically connected to the first through electrode. A second redistribution part is disposed over the first surface and includes a second redistribution layer electrically connected to the first bond pad.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: November 18, 2014
    Inventors: Do Hyung Kim, Dae Byoung Kang, Seung Chul Han
  • Patent number: 8441123
    Abstract: A semiconductor device has a first semiconductor die having at least one metal pillar formed along an inner perimeter and at least one bond pad formed along an outer perimeter. A second semiconductor die has at least one metal pillar. A conductive bump connects the at least one metal pillar of the first semiconductor die to the at least one metal pillar of the second semiconductor die. At least one metal dam is formed on the first semiconductor die between the at least one metal pillar of the first semiconductor die and the at least one bond pad.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: May 14, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Dong Hee Lee, Min Yoo, Dae Byoung Kang, Bae Yong Kim
  • Publication number: 20120273946
    Abstract: A semiconductor device entirely having a small height, which performs a fan-out operation for input/output signals and forms a short electrical path is provided. The semiconductor device includes a first semiconductor die having a first surface, a second surface opposed to the first surface, a third surface connecting the first and second surfaces to each other, a first bond pad disposed on the first surface, and a first through electrode passing between the first surface and second surface and electrically connected to the first bond pad. A first redistribution part is disposed under the second surface and includes a first redistribution layer electrically connected to the first through electrode. A second redistribution part is disposed over the first surface and includes a second redistribution layer electrically connected to the first bond pad.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Inventors: Do Hyung Kim, Dae Byoung Kang, Seung Chul Han
  • Patent number: 8089145
    Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads are provided in two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: January 3, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Gwang Ho Kim, Jin Seong Kim, Dong Joo Park, Dae Byoung Kang
  • Patent number: 7982298
    Abstract: In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In certain embodiments, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. One or more of the semiconductor dies may include through-silicon vias formed therein for facilitating the electrical connection thereof to the conductive pattern of the substrate or to other electronic components within the vertical stack. Similarly, the semiconductor package may be provided with through-mold vias to facilitate the electrical connection thereof to other electronic components within the vertical stack.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: July 19, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Dae Byoung Kang, Sung Jin Yang, Jung Tae Ok, Jae Dong Kim
  • Patent number: 6897550
    Abstract: A memory card comprising a leadframe having at least one die pad, a plurality of contacts, and a plurality of conductive traces extending from respective ones of the contacts toward the die pad. The traces are bent in a manner wherein the die pad and the contacts extend along respective ones of spaced, generally parallel frame planes. Disposed on and extending from the die pad and the traces is a plurality of stand-offs. At least one semiconductor die is attached to the die pad and electrically connected to at least one of the traces. A body at least partially encapsulates the leadframe and the semiconductor die such that the contacts are exposed in a bottom surface defined by the body.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: May 24, 2005
    Assignee: Amkor Technology, Inc.
    Inventors: Curtis M. Zwenger, Raul M. Guerrero, Dae Byoung Kang, Chul Woo Park