Abstract: Provided is a super junction semiconductor device. The super junction semiconductor device includes a vertical pillar region located in an active region and horizontal pillar regions located in a termination region that are connected with each other while simultaneously not floating the entire pillar region in the termination region. Thus, a charge compensation difference, generated among pillar regions, is caused to be offset, although the length of the termination region is relatively short.

Abstract: There is provided a super junction semiconductor device. The super junction semiconductor device includes a cell area and a junction termination area disposed on a substrate, and a transition area disposed between the cell area and the junction termination area, and the cell area, the junction termination area, and the transition area each include one or more unit cells comprising a N-type pillar region and a P-type pillar region among a plurality of N-type pillar regions and a P-type pillar regions that are alternated between the cell area and the junction termination area.

Abstract: Provided is a super junction semiconductor device. The super junction semiconductor device includes a vertical pillar region located in an active region and horizontal pillar regions located in a termination region that are connected with each other while simultaneously not floating the entire pillar region in the termination region. Thus, a charge compensation difference, generated among pillar regions, is caused to be offset, although the length of the termination region is relatively short.

Abstract: There is provided a super junction semiconductor device. The super junction semiconductor device includes a cell area and a junction termination area disposed on a substrate, and a transition area disposed between the cell area and the junction termination area, and the cell area, the junction termination area, and the transition area each include one or more unit cells comprising a N-type pillar region and a P-type pillar region among a plurality of N-type pillar regions and a P-type pillar regions that are alternated between the cell area and the junction termination area.

Abstract: The semiconductor device and the method for fabricating the same includes a trench formed with a predetermined depth in a region of a substrate. A device isolation film is formed as a sidewall type spacers at both sides of the trench. A second conductivity type semiconductor film is formed in the trench. A second conductivity type transistor is formed in first and second regions of the substrate, and a first conductivity type transistor formed in a third region of the substrate.