Patents by Inventor Dae-Cheol Seong
Dae-Cheol Seong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11721640Abstract: An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.Type: GrantFiled: December 7, 2021Date of Patent: August 8, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-gu Kang, Young-mok Kim, Woon-bae Kim, Dae-cheol Seong, Yune-seok Chung
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Publication number: 20220093527Abstract: An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.Type: ApplicationFiled: December 7, 2021Publication date: March 24, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-gu KANG, Young-mok KIM, Woon-bae KIM, Dae-cheol SEONG, Yune-seok CHUNG
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Patent number: 11222853Abstract: An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.Type: GrantFiled: October 1, 2019Date of Patent: January 11, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-gu Kang, Young-mok Kim, Woon-bae Kim, Dae-cheol Seong, Yune-seok Chung
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Patent number: 11121127Abstract: An integrated circuit chip includes a circuit structure, a grounding structure, a bonding layer between the circuit structure and the grounding structure. The circuit structure includes a first substrate, an FEOL structure, and a BEOL structure. The grounding structure includes a second substrate and a grounding conductive layer. The integrated circuit chip includes a first penetrating electrode portion connected to the grounding conductive layer based on extending through the first substrate, the FEOL structure, the BEOL structure, and the bonding layer such that the first penetrating electrode portion is isolated from direct contact with the integrated circuit portion in a horizontal direction extending parallel to an active surface of the first substrate. An integrated circuit package and a display device each include the integrated circuit chip.Type: GrantFiled: October 1, 2019Date of Patent: September 14, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-gu Kang, Young-mok Kim, Woon-bae Kim, Dae-cheol Seong, Yune-seok Chung
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Publication number: 20200235091Abstract: An integrated circuit chip includes a circuit structure, a grounding structure, a bonding layer between the circuit structure and the grounding structure. The circuit structure includes a first substrate, an FEOL structure, and a BEOL structure. The grounding structure includes a second substrate and a grounding conductive layer. The integrated circuit chip includes a first penetrating electrode portion connected to the grounding conductive layer based on extending through the first substrate, the FEOL structure, the BEOL structure, and the bonding layer such that the first penetrating electrode portion is isolated from direct contact with the integrated circuit portion in a horizontal direction extending parallel to an active surface of the first substrate. An integrated circuit package and a display device each include the integrated circuit chip.Type: ApplicationFiled: October 1, 2019Publication date: July 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: JUNG-GU KANG, Young-mok Kim, Woon-bae Kim, Dae-cheol Seong, Yune-seok Chung
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Publication number: 20200227359Abstract: An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.Type: ApplicationFiled: October 1, 2019Publication date: July 16, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-gu KANG, Young-mok KIM, Woon-bae KIM, Dae-cheol SEONG, Yune-seok CHUNG
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Patent number: 8354292Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.Type: GrantFiled: March 6, 2012Date of Patent: January 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Patent number: 8309996Abstract: Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and methods of manufacturing the same are provided, the sensors include an epitaxial layer on a substrate in which a first, second, third and fourth region are defined. A photodiode may be formed at an upper portion of the epitaxial layer in the first region. A plurality of gate structures may be formed on the epitaxial layer in the second, third and fourth regions. A first blocking layer may be formed on the gate structures and the epitaxial layer in the first and second regions. A first impurity layer may be formed at an upper portion of the epitaxial layer adjacent to the gate structures in the second region, and a second impurity layer at upper portions of the epitaxial layer adjacent to the gate structures in the third and fourth regions. A color filter layer may be formed over the photodiode. A microlens may be formed on the color filter layer.Type: GrantFiled: March 16, 2011Date of Patent: November 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ui-Sik Kim, Young-Hoon Park, Won-Je Park, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Publication number: 20120164783Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.Type: ApplicationFiled: March 6, 2012Publication date: June 28, 2012Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Patent number: 8138530Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.Type: GrantFiled: June 11, 2009Date of Patent: March 20, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Keang
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Publication number: 20110204468Abstract: Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning the gate insulating film and the gate conductive film; and fabricating a transfer gate electrode by forming a first-conductive-type photodiode in the semiconductor substrate adjacent to one region of the transfer gate pattern, by forming a second-conductive-type photodiode on the first-conductive-type photodiode, and by forming a first-conductive-type floating diffusion region in the semiconductor substrate adjacent to the other region of the transfer gate pattern.Type: ApplicationFiled: April 26, 2011Publication date: August 25, 2011Inventors: Jae-ho Song, Chan Park, Young-hoon Park, Sang-il Jung, Jong-wook Hong, Keo-sung Park, Eun-soo Kim, Won-je Park, Jin-Hyeong Park, Dae-cheol Seong, Won-jeong Lee, Pu-ra Kim
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Publication number: 20110163363Abstract: Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and methods of manufacturing the same are provided, the sensors include an epitaxial layer on a substrate in which a first, second, third and fourth region are defined. A photodiode may be formed at an upper portion of the epitaxial layer in the first region. A plurality of gate structures may be formed on the epitaxial layer in the second, third and fourth regions. A first blocking layer may be formed on the gate structures and the epitaxial layer in the first and second regions. A first impurity layer may be formed at an upper portion of the epitaxial layer adjacent to the gate structures in the second region, and a second impurity layer at upper portions of the epitaxial layer adjacent to the gate structures in the third and fourth regions. A color filter layer may be formed over the photodiode. A microlens may be formed on the color filter layer.Type: ApplicationFiled: March 16, 2011Publication date: July 7, 2011Inventors: Ui-Sik Kim, Young-Hoon Park, Won-Je Park, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Patent number: 7955924Abstract: Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning the gate insulating film and the gate conductive film; and fabricating a transfer gate electrode by forming a first-conductive-type photodiode in the semiconductor substrate adjacent to one region of the transfer gate pattern, by forming a second-conductive-type photodiode on the first-conductive-type photodiode, and by forming a first-conductive-type floating diffusion region in the semiconductor substrate adjacent to the other region of the transfer gate pattern.Type: GrantFiled: January 10, 2007Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-ho Song, Chan Park, Young-hoon Park, Sang-il Jung, Jong-wook Hong, Keo-sung Park, Eun-soo Kim, Won-je Park, Jin-Hyeong Park, Dae-cheol Seong, Won-jeong Lee, Pu-ra Kim
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Patent number: 7932120Abstract: Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and methods of manufacturing the same are provided, the sensors include an epitaxial layer on a substrate in which a first, second, third and fourth region are defined. A photodiode may be formed at an upper portion of the epitaxial layer in the first region. A plurality of gate structures may be formed on the epitaxial layer in the second, third and fourth regions. A first blocking layer may be formed on the gate structures and the epitaxial layer in the first and second regions. A first impurity layer may be formed at an upper portion of the epitaxial layer adjacent to the gate structures in the second region, and a second impurity layer at upper portions of the epitaxial layer adjacent to the gate structures in the third and fourth regions. A color filter layer may be formed over the photodiode. A microlens may be formed on the color filter layer.Type: GrantFiled: August 27, 2009Date of Patent: April 26, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Ui-Sik Kim, Young-Hoon Park, Won-Je Park, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Publication number: 20100055823Abstract: Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and methods of manufacturing the same are provided, the sensors include an epitaxial layer on a substrate in which a first, second, third and fourth region are defined. A photodiode may be formed at an upper portion of the epitaxial layer in the first region. A plurality of gate structures may be formed on the epitaxial layer in the second, third and fourth regions. A first blocking layer may be formed on the gate structures and the epitaxial layer in the first and second regions. A first impurity layer may be formed at an upper portion of the epitaxial layer adjacent to the gate structures in the second region, and a second impurity layer at upper portions of the epitaxial layer adjacent to the gate structures in the third and fourth regions. A color filter layer may be formed over the photodiode. A microlens may be formed on the color filter layer.Type: ApplicationFiled: August 27, 2009Publication date: March 4, 2010Inventors: Ui-Sik Kim, Young-Hoon Park, Won-Je Park, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Publication number: 20090309144Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.Type: ApplicationFiled: June 11, 2009Publication date: December 17, 2009Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Keang
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Publication number: 20070161140Abstract: Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning the gate insulating film and the gate conductive film; and fabricating a transfer gate electrode by forming a first-conductive-type photodiode in the semiconductor substrate adjacent to one region of the transfer gate pattern, by forming a second-conductive-type photodiode on the first-conductive-type photodiode, and by forming a first-conductive-type floating diffusion region in the semiconductor substrate adjacent to the other region of the transfer gate pattern.Type: ApplicationFiled: January 10, 2007Publication date: July 12, 2007Inventors: Jae-ho Song, Chan Park, Young-hoon Park, Sang-il Jung, Jong-wook Hong, Keo-sung Park, Eun-soo Kim, Won-je Park, Jin-Hyeong Park, Dae-cheol Seong, Won-jeong Lee, Pu-ra Kim