Patents by Inventor Dae-Chul JEONG

Dae-Chul JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949881
    Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: April 2, 2024
    Assignees: Electronics and Telecommunications Research Institute, Kwangwoon University Research Institute for Industry Cooperation, Industry-Academia Cooperation Group of Sejong University
    Inventors: Se-Yoon Jeong, Hae-Chul Choi, Jeong-Il Seo, Seung-Kwon Beack, In-Seon Jang, Jae-Gon Kim, Kyung-Ae Moon, Dae-Young Jang, Jin-Woo Hong, Jin-Woong Kim, Yung-Lyul Lee, Dong-Gyu Sim, Seoung-Jun Oh, Chang-Beom Ahn, Dae-Yeon Kim, Dong-Kyun Kim
  • Patent number: 11931431
    Abstract: The present invention relates to a pharmaceutical composition for diagnosing and treating prostate cancer, capable of targeting PSMA, and a compound provided by one aspect of the present invention has a glutamine-urea-lysine compound to which a radioactive metal-coupled chelator is structurally coupled and to which an aryl group that can additionally bind to PSMA protein is coupled. Coupling between the glutamine-urea-lysine compound and the chelator includes a polar spacer so as to serve the role of reducing in vivo nonspecific coupling and exhibit an effect of being rapidly removed from vital organs, but not from prostate cancer. These characteristics lower the radiation exposure, which is caused by a therapeutic radioisotope-coupled compound, to normal tissue and organs, and thus reduce side effects. In addition, a compound that contains a phenyl group having a coupling force with albumin has an increased residence time in the blood, thereby becoming more accumulated in prostate cancer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 19, 2024
    Assignee: FUTURECHEM CO., LTD
    Inventors: Dae Yoon Chi, Byoung Se Lee, So Young Chu, Hyeon Jin Jeong, Min Hwan Kim, Kyo Chul Lee, Yong Jin Lee
  • Publication number: 20240085282
    Abstract: There is provide a method for manufacturing analytical semiconductor samples by using an apparatus for manufacturing analytical semiconductor samples, which minimizes a feedback time by manufacturing a viewing surface that is environment-friendly and has a large area. The method comprising mounting the analytical semiconductor samples to a holder; discharging deionized (DI) water to an upper surface of a polishing plate through a DI water nozzle; grinding the analytical semiconductor samples with the upper surface of the polishing plat; determining whether a desired viewing surface of the analytical semiconductor samples has been acquired after the grinding of the analytical semiconductor samples; and transferring the analytical semiconductor samples to analyze the viewing surface of the ground analytical semiconductor samples based on a determination that the desired viewing surface of the analytical semiconductor samples has been acquired.
    Type: Application
    Filed: August 23, 2023
    Publication date: March 14, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min Chul JO, Sang Hyun PARK, Su Jin SHIN, Gil Ho GU, Dae Gon YU, So Yeon LEE, Yun Bin JEONG
  • Patent number: 9722829
    Abstract: A pulse shaping circuit is configured to shape a waveform of an edge of a signal applied to a switch of a power amplifier included in an on-off keying transmitter.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: August 1, 2017
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Jae Sup Lee, Bum Man Kim, Han-Kyu Lee, Dae Chul Jeong, Tae Young Chung
  • Patent number: 9667241
    Abstract: A leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: May 30, 2017
    Assignees: Samsung Electronics Co., Ltd., Poshtech Academy-Industry Foundation
    Inventors: Jaesup Lee, Tae-Young Chung, Bum-Man Kim, Dae-Chul Jeong
  • Patent number: 9436202
    Abstract: A power circuit for reducing a leakage power using a negative voltage is provided. The power circuit includes a current source including a transistor including a gate. The power circuit further includes a current source control circuit connected to the gate of the transistor, and configured to apply a positive voltage to the gate of the transistor if the current source is to operate in an active mode, and apply the negative voltage to the gate of the transistor if the current source is to operate in an inactive mode.
    Type: Grant
    Filed: November 17, 2012
    Date of Patent: September 6, 2016
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Jae Sup Lee, Seong Joong Kim, Bum Man Kim, Han-Kyu Lee, Dae-Chul Jeong, Tae Young Chung
  • Publication number: 20160241229
    Abstract: A leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.
    Type: Application
    Filed: September 24, 2015
    Publication date: August 18, 2016
    Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaesup LEE, Tae-Young CHUNG, Bum-Man KIM, Dae-Chul JEONG
  • Publication number: 20150139362
    Abstract: A pulse shaping circuit is configured to shape a waveform of an edge of a signal applied to a switch of a power amplifier included in an on-off keying transmitter.
    Type: Application
    Filed: February 26, 2014
    Publication date: May 21, 2015
    Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Sup LEE, Bum Man KIM, Han-Kyu LEE, Dae Chul JEONG, Tae Young CHUNG
  • Publication number: 20130193948
    Abstract: A power circuit for reducing a leakage power using a negative voltage is provided. The power circuit includes a current source including a transistor including a gate. The power circuit further includes a current source control circuit connected to the gate of the transistor, and configured to apply a positive voltage to the gate of the transistor if the current source is to operate in an active mode, and apply the negative voltage to the gate of the transistor if the current source is to operate in an inactive mode.
    Type: Application
    Filed: November 17, 2012
    Publication date: August 1, 2013
    Inventors: Jae Sup LEE, Seong Joong KIM, Bum Man KIM, Han-Kyu LEE, Dae-Chul JEONG, Tae Young CHUNG