Patents by Inventor Dae Gon Yun

Dae Gon Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8026516
    Abstract: Provided is a carrier module for use in a handler for handling a packaged chip for a test, the carrier module including a body provided, a base plate where the packaged chips are placed, provided to the body, and at least one latch which holds the packaged chips in position in the base plate.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: September 27, 2011
    Assignee: Mirae Corporation
    Inventors: Jung Ug An, Hee Rak Beom, Dae Gon Yun
  • Patent number: 7583076
    Abstract: A semiconductor chip test handler includes a first chamber in which packaged chips contained in a test tray are heated to high temperature or cooled to low temperature, a second chamber in which the packaged chips contained in the test tray are tested, and a third chamber in which the packaged chips contained in the test tray are cooled or heated to room temperature. The test trays are horizontally and/or vertically moved in an upright position between the first, second, and third chambers. The chambers may be arranged in a row or in a column. The test trays include a frame and a plurality of carriers into which the packaged chips are loaded. Connecting member and or projections are detachably mounted on lateral sides of the frame. A moving apparatus for moving the test trays between the first, second, and third chambers uses the connecting members and projections to push or pull the test trays into and out of the chambers.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: September 1, 2009
    Assignee: Mirae Corporation
    Inventors: Yong Sun Kim, Hyo Chul Yun, Dae Gon Yun
  • Publication number: 20080186047
    Abstract: Provided is a sorting system for handling packaged chips for testing and sorting the packaged chips by grade, capable of performing loading and unloading operations, independently of a testing operation. The sorting system includes a loading unit including a loading picker, an unloading unit provided adjacent to the loading unit, a rack in which to store at least one test tray containing the packaged chips intended for the tests and at least one test tray containing the tested packaged chips, an exchanging site where the test tray containing the packaged chips intended for the tests and the test tray containing the tested packaged chips are exchanged with the rack, and a transferring unit transferring the test tray between the loading position, the exchanging site, and the unloading position.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 7, 2008
    Inventors: Hee Rak Beom, Dae Gon Yun, Yong Geun Park
  • Publication number: 20080174299
    Abstract: A semiconductor chip test handler includes a first chamber in which packaged chips contained in a test tray are heated to high temperature or cooled to low temperature, a second chamber in which the packaged chips contained in the test tray are tested, and a third chamber in which the packaged chips contained in the test tray are cooled or heated to room temperature. The test trays are horizontally and/or vertically moved in an upright position between the first, second, and third chambers. The chambers may be arranged in a row or in a column. The test trays include a frame and a plurality of carriers into which the packaged chips are loaded. Connecting member and or projections are detachably mounted on lateral sides of the frame. A moving apparatus for moving the test trays between the first, second, and third chambers uses the connecting members and projections to push or pull the test trays into and out of the chambers.
    Type: Application
    Filed: January 22, 2008
    Publication date: July 24, 2008
    Inventors: Yong Sun KIM, Hyo Chul Yun, Dae Gon Yun
  • Publication number: 20080145203
    Abstract: Provided is a method for transferring test trays in a handler including a second chamber having two test sites arranged in parallel, a first chamber having a plurality of passages along which a plurality of test trays are horizontally moved, provided over the second chamber, and a third chamber having a plurality of passages along which the plurality of test trays are horizontally moved, provided under the second chamber, the method including steps of (a) enabling two test trays to wait in parallel in a horizontal position at a waiting location provided to a forward section of the handler, (b) loading packaged chips onto the two test trays, (c) rotating the two test trays to be in the upright position, (d) moving upwards the two test trays into the first chamber, (e) heating or cooling the two test trays while moving horizontally the two test trays forward in the first chamber, (f) moving downward the two test trays from the first chamber into the second chamber, (g) moving horizontally the two test trays tow
    Type: Application
    Filed: November 21, 2007
    Publication date: June 19, 2008
    Inventors: Hyo-chul YUN, Hee-rak Beom, Jae-myeong Song, Yong-geun Park, Dae-gon Yun
  • Publication number: 20080121561
    Abstract: Provided is a carrier module for use in a handler for handling a packaged chip for a test, the carrier module including a body provided, a base plate where the packaged chips are placed, provided to the body, and at least one latch which holds the packaged chips in position in the base plate.
    Type: Application
    Filed: November 28, 2007
    Publication date: May 29, 2008
    Inventors: Jung Ug An, Hee Rak Beom, Dae Gon Yun