Patents by Inventor Dae Gyn Park

Dae Gyn Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CMOS of semiconductor device and method for manufacturing the same
    Publication number: 20040061150
    Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.
    Type: Application
    Filed: September 17, 2003
    Publication date: April 1, 2004
    Applicant: Hynix Semiconductor Inc.
    Inventors: Heung Jae Cho, Dae Gyn Park, Kwan Yong Lim