Abstract: Disclosed is a wearable device. A wearable device may include a driving module, a first frame corresponding to a portion of a lower body of a user, an angle sensor configured to sense an angle of the first frame and obtain a first frame angle value, a lumbar support module connected to the driving module and positioned on a lower back area of the user, an inertial measurement unit (IMU) sensor, and a processor(s). The processor(s) may be configured to obtain the first frame angle value using the angle sensor, obtain a first rotation angle value of the lumbar support module using the IMU sensor, determine whether a sitting posture of the user is an abnormal sitting posture based on the first rotation angle value and the first frame angle value, and control the driving module such that the driving module generates a first torque when determining that the sitting posture is the abnormal sitting posture.

Abstract: An apparatus for warning vehicle entry into a dangerous area includes: a monitoring period calculator determining a first monitoring period based on a driving speed of a vehicle and a distance from the vehicle to a second dangerous area nearest to the vehicle after an initial first alarm is transmitted as the vehicle enters a first dangerous area; a dangerous area entry detector determining whether the vehicle enters the dangerous area in every first monitoring period; and an alarm transmitter transmitting a second alarm when the vehicle entry into the second dangerous area is detected.

Abstract: According to various embodiments, an electronic device may include: a communication processor, a radio frequency (RF) integrated circuit (RFIC) configured to receive a signal output from the communication processor and to modulate the signal into an RF signal, a power management circuit, a first power amplifier configured to amplify an RF signal output from the RFIC based on power supplied from the power management circuit, a second power amplifier configured to amplify the RF signal output from the RFIC based on the power supplied from the power management circuit, at least one capacitor connected in parallel to a power supply terminal of the first power amplifier, and at least one switch connected between the power supply terminal and the at least one capacitor, wherein the communication processor is configured to: identify a power amplification mode based a frequency band of the RF signal, and control the at least one switch by outputting a control signal corresponding to the identified power amplification

Abstract: A method for forming a semiconductor structure. Two isolation structures are formed in a semiconductor. A cavity is etched in the semiconductor between the two isolation structures in the semiconductor. Dopants are implanted into a bottom side of the cavity to form a doped region in the semiconductor below the cavity between the two isolation structures. A contact is formed in the cavity. The contact is on the doped region and in direct contact with the doped region.

Abstract: According to various embodiments, an electronic device may include: a communication processor, a radio frequency (RF) integrated circuit (RFIC) configured to receive a signal output from the communication processor and to modulate the signal into an RF signal, a power management circuit, a first power amplifier configured to amplify an RF signal output from the RFIC based on power supplied from the power management circuit, a second power amplifier configured to amplify the RF signal output from the RFIC based on the power supplied from the power management circuit, at least one capacitor connected in parallel to a power supply terminal of the first power amplifier, and at least one switch connected between the power supply terminal and the at least one capacitor, wherein the communication processor is configured to: identify a power amplification mode based a frequency band of the RF signal, and control the at least one switch by outputting a control signal corresponding to the identified power amplification

Abstract: A method for forming a semiconductor structure. Two isolation structures are formed in a semiconductor. A cavity is etched in the semiconductor between the two isolation structures in the semiconductor. Dopants are implanted into a bottom side of the cavity to form a doped region in the semiconductor below the cavity between the two isolation structures. A contact is formed in the cavity. The contact is on the doped region and in direct contact with the doped region.

Abstract: A method for etching features into an etch layer disposed below a photoresist mask without an intermediate hardmask is provided. A plurality of etch cycles are provided. Each etch cycle comprises providing a deposition etch phase that etches features into the etch layer and deposits polymer on sidewalls of the features and over the photoresist and providing a cleaning phase that removes polymer deposited on the sidewalls.

Abstract: A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.

Abstract: A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.

Abstract: A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.

Abstract: A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.

Abstract: A method for etching features into an etch layer disposed below a photoresist mask without an intermediate hardmask is provided. A plurality of etch cycles are provided. Each etch cycle comprises providing a deposition etch phase that etches features into the etch layer and deposits polymer on sidewalls of the features and over the photoresist and providing a cleaning phase that removes polymer deposited on the sidewalls.

Abstract: A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.

Abstract: A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.