Patents by Inventor Daehan Choi
Daehan Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922648Abstract: An electronic device and method are provided for obtaining an image. An electronic device may include cameras; a distance sensor including a light-emitting part and a light-receiving part; and a processor.Type: GrantFiled: May 13, 2022Date of Patent: March 5, 2024Assignee: Samsung Electronics Co., LtdInventors: Gwangho Choi, Sungeun Kim, Hanul Moon, Insun Song, Daehan Wi, Sunggeun Yim
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Publication number: 20220368358Abstract: According to various embodiments, an electronic device may include: a communication processor, a radio frequency (RF) integrated circuit (RFIC) configured to receive a signal output from the communication processor and to modulate the signal into an RF signal, a power management circuit, a first power amplifier configured to amplify an RF signal output from the RFIC based on power supplied from the power management circuit, a second power amplifier configured to amplify the RF signal output from the RFIC based on the power supplied from the power management circuit, at least one capacitor connected in parallel to a power supply terminal of the first power amplifier, and at least one switch connected between the power supply terminal and the at least one capacitor, wherein the communication processor is configured to: identify a power amplification mode based a frequency band of the RF signal, and control the at least one switch by outputting a control signal corresponding to the identified power amplificationType: ApplicationFiled: May 12, 2022Publication date: November 17, 2022Inventors: Kyujae JANG, Cheonshik KIM, Juho VAN, Jonghyeok IM, Daeyoung JO, Youngjune HONG, Daehan CHOI, Hyeyong GO, Yeongseob LIM, Sungyoul CHO, Taekyoung JIN
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Publication number: 20220028989Abstract: A method for forming a semiconductor structure. Two isolation structures are formed in a semiconductor. A cavity is etched in the semiconductor between the two isolation structures in the semiconductor. Dopants are implanted into a bottom side of the cavity to form a doped region in the semiconductor below the cavity between the two isolation structures. A contact is formed in the cavity. The contact is on the doped region and in direct contact with the doped region.Type: ApplicationFiled: June 8, 2021Publication date: January 27, 2022Inventors: Kangmu Min Lee, Maxwell Daehan Choi, Jeffrey Alden Wright, Wonill Ha, Clayton Jackson, Michael Pemberton Jura, Adele Schmitz, James Chappell
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Patent number: 7910489Abstract: A method for etching features into an etch layer disposed below a photoresist mask without an intermediate hardmask is provided. A plurality of etch cycles are provided. Each etch cycle comprises providing a deposition etch phase that etches features into the etch layer and deposits polymer on sidewalls of the features and over the photoresist and providing a cleaning phase that removes polymer deposited on the sidewalls.Type: GrantFiled: February 17, 2006Date of Patent: March 22, 2011Assignee: Lam Research CorporationInventors: Ji Soo Kim, Peter Cirigliano, Sangheon Lee, Dongho Heo, Daehan Choi, S. M. Reza Sadjadi
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Patent number: 7560388Abstract: A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.Type: GrantFiled: November 30, 2005Date of Patent: July 14, 2009Assignee: Lam Research CorporationInventors: Jisoo Kim, Sangheon Lee, Daehan Choi, S. M. Reza Sadjadi
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Patent number: 7476610Abstract: A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.Type: GrantFiled: November 10, 2006Date of Patent: January 13, 2009Assignee: Lam Research CorporationInventors: Ji Soo Kim, Conan Chiang, Daehan Choi, S. M. Reza Sadjadi, Michael Goss
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Patent number: 7390749Abstract: A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.Type: GrantFiled: November 9, 2006Date of Patent: June 24, 2008Assignee: Lam Research CorporationInventors: Ji Soo Kim, Sangheon Lee, Daehan Choi, S. M. Reza Sadjadi
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Publication number: 20080111166Abstract: A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.Type: ApplicationFiled: November 10, 2006Publication date: May 15, 2008Inventors: Ji Soo Kim, Conan Chiang, Daehan Choi, S. M. Reza Sadjadi, Michael Goss
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Publication number: 20070193973Abstract: A method for etching features into an etch layer disposed below a photoresist mask without an intermediate hardmask is provided. A plurality of etch cycles are provided. Each etch cycle comprises providing a deposition etch phase that etches features into the etch layer and deposits polymer on sidewalls of the features and over the photoresist and providing a cleaning phase that removes polymer deposited on the sidewalls.Type: ApplicationFiled: February 17, 2006Publication date: August 23, 2007Inventors: Ji Kim, Peter Cirigliano, Sangheon Lee, Dongho Heo, Daehan Choi, S. Sadjadi
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Publication number: 20070123053Abstract: A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.Type: ApplicationFiled: November 30, 2005Publication date: May 31, 2007Inventors: Jisoo Kim, Sangheon Lee, Daehan Choi, S.M. Sadjadi
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Publication number: 20070122977Abstract: A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.Type: ApplicationFiled: November 9, 2006Publication date: May 31, 2007Inventors: Ji Kim, Sangheon Lee, Daehan Choi, S. Sadjadi