Abstract: [summary] An epitaxial wafer is disclosed. The epitaxial wafer includes a substrate; and a stack disposed on the substrate, wherein the stack includes silicon (Si) layers and silicon germanium (SiGe) layers alternately stacked on top of each other, wherein the silicon germanium layer is doped with boron (B) or phosphorus (P).

Abstract: A nonvolatile resistive switching memory (ReRAM) device having no selection device is provided. The ReRAM device includes a lower electrode that is formed on on a substrate; a metal oxide layer that is formed on the lower electrode, the metal oxide layer having a resistive switching characteristic; an upper electrode that is formed on the metal oxide layer; and a tunnel barrier oxide film that is formed between the lower electrode and the metal oxide layer, thereby forming a double oxide film structure, the tunnel barrier oxide film being made of a material, a band energy gap and a conduction band offset of which are lower than those of the metal oxide layer, and which does not cause interface switching.

Abstract: Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.

Abstract: A memory device includes a substrate and a memory cell including a first electrode on the substrate, a phase-change material region on the first electrode and a second electrode on the phase-change material region opposite the first electrode. The memory device further includes a stress relief buffer adjacent a sidewall of the phase-change material region between the first and second electrodes. In some embodiments, the stress relief buffer includes a stress relief region contacting the sidewall of the phase-change material region. In further embodiments, the stress relief buffer includes a void adjacent the sidewall of the phase-change material region.

Abstract: Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: A tungsten or other metal layer is chemical vapor deposited using a source gas containing tungsten, a reducing gas and a nitrogen-containing gas. The nitrogen-containing gas can act as a surface roughness reducing gas that reduces the roughness of the tungsten layer compared to a tungsten layer that is chemical vapor deposited using the source gas containing tungsten and the reducing gas, but without using the surface roughness reducing gas. Viewed in another way, the nitrogen-containing gas acts as a growth rate controlling gas that produces uniform growth of the tungsten layer in a plurality of directions compared to a tungsten layer that is deposited using the source gas containing tungsten and the reducing gas, but without using the growth rate controlling gas.

Abstract: Methods for fabricating a tungsten nitride layer in a semiconductor substrate having an insulating layer formed thereon. The methods include forming a contact hole through the insulating layer. A tungsten nitride layer is then selectively deposited only in the contact hole by selectively reacting a nitrogen-containing gas with a tungsten source gas so as to prevent formation of tungsten nitride layer on the insulating layer outside the contact hole. Methods or fabricating metal wiring utilizing the methods of fabricating a tungsten nitride layer are also provided.

Abstract: A method of manufacturing a semiconductor capacitor electrode by growing a metal compound layer over polysilicon storage nodes. The metal compound layer readily growing on the polysilicon storage nodes, but not on portions of an insulating layer between adjacent polysilicon storage nodes.

Abstract: A gate electrode in a semiconductor device comprising; a gate oxide layer formed on a semiconductor substrate, a polysilicon layer formed on the gate oxide layer, a silicide layer formed on the polysilicon layer and, a metal silicide layer formed on the silicide layer.

Abstract: There is provided a method for manufacturing a capacitor in a semiconductor device including the steps of forming first and second insulating layers with a first contact hole through to a semiconductor substrate, patterning a first conductive layer to form a pedestal portion of a lower electrode, using a patterned third insulating layer selectively forming an upper portion of the lower electrode from a tungsten nitride thin film, and forming an undercut beneath the pedestal portion by wet-etching the second insulating layer.