Patents by Inventor Dae-Hoon Bae

Dae-Hoon Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertical memory devices having dummy channel regions
    Patent number: 10153292
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, Hanmei Choi
  • VERTICAL MEMORY DEVICES HAVING DUMMY CHANNEL REGIONS
    Publication number: 20180190668
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Inventors: JONG WON KIM, SEUNG HYUN LIM, CHANG SEOK KANG, YOUNG WOO PARK, DAE HOON BAE, DONG SEOG EUN, WOO SUNG LEE, JAE DUK LEE, JAE WOO LIM, HANMEI CHOI
  • Vertical memory devices having dummy channel regions
    Patent number: 9972636
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: May 15, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, Hanmei Choi
  • VERTICAL MEMORY DEVICES HAVING DUMMY CHANNEL REGIONS
    Publication number: 20170294443
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 12, 2017
    Inventors: JONG WON KIM, SEUNG HYUN LIM, CHANG SEOK KANG, YOUNG WOO PARK, DAE HOON BAE, DONG SEOG EUN, WOO SUNG LEE, JAE DUK LEE, JAE WOO LIM, HANMEI CHOI
  • Vertical memory devices having dummy channel regions
    Patent number: 9716104
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: July 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, HanMei Choi
  • VERTICAL MEMORY DEVICES HAVING DUMMY CHANNEL REGIONS
    Publication number: 20170040337
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Application
    Filed: January 5, 2016
    Publication date: February 9, 2017
    Inventors: Jong Won KIM, Seung Hyun LIM, Chang Seok KANG, Young Woo PARK, Dae Hoon BAE, Dong Seog EUN, Woo Sung LEE, Jae Duk LEE, Jae Woo LIM, HanMei CHOI
  • Method for manufacturing semiconductor device with stagnated process gas
    Patent number: 6284632
    Abstract: According to the present invention, a process of the present invention is performed with stagnated process gas in a chamber. The process comprises the steps of supplying process gas into a chamber, blocking process gas entry and exit from the chamber so as to stagnate the supplied gas therein, and performing the process. As a result, a process time can be significantly reduced, thereby maximizing yield and reducing the substantial amount of the process gas.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: September 4, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Jin Lee, Jae-Chul Lee, Hyun-Bo Shin, Dae-Hoon Bae