Patents by Inventor Dae-hoon Kim

Dae-hoon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6247813
    Abstract: An iris identification system and method of identifying the identity of an animate being through iris scanning are disclosed. The system features an iris system pick-up unit including a camera for capturing iris images to create input image signals. The iris image pick-up unit is operated with a control unit that is interfaced with a data processing unit for preprocessing the input image signals into processed data. The processed data is representative of one of a plurality of parameters for iris identification selected from the group consisting of (1) the density and texture form of the iris fiber structure using a frequency transformation method, (2) pupilliary reaction, (3) the shape of the pupil, (4) autonomous nervous wreath reaction, (5) shape of the autonomous nervous wreath, (6) the existence of lacuna, (7) the location of the lacuna, and (8) the shape of the lacuna.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: June 19, 2001
    Assignee: IriTech, Inc.
    Inventors: Dae Hoon Kim, Jang Soo Ryoo
  • Patent number: 6232228
    Abstract: A method of manufacturing semiconductor devices is provided, including the formation of a conductive plug and the minimizing of the step-height of an interlayer dielectric layer. An etching composition is also provided for such a manufacturing method. The method of manufacturing semiconductor devices includes the steps of forming an insulating layer over a semiconductor substrate, forming contact holes in the insulating layer, forming a conductive layer over the insulating layer to burying the contact holes, rotating the semiconductor substrate, and etching the conductive layer by supplying an etching composition on the rotating semiconductor substrate, and spin-etching the tungsten layer using an etching composition such that the conductive layer remains only inside the contact holes and does not remain over the insulating layer.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: May 15, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-hwan Kwag, Se-jong Ko, Kyung-seuk Hwang, Jun-ing Gil, Sang-o Park, Dae-hoon Kim, Sang-moon Chon, Ho-Kyoon Chung
  • Patent number: 6140233
    Abstract: A method of manufacturing semiconductor devices is provided for forming a tungsten plug or polysilicon plug and minimizing the step-height of the intermediate insulating layer. An etching composition for this process is also provided as are semiconductor devices manufactured by this process. The method of manufacturing semiconductor devices includes the steps of forming a tungsten film having a certain thickness on an insulating layer and burying contact holes formed in the insulating layer constituting a specific semiconductor structure, and spin-etching the tungsten film using a certain etching composition such that the tungsten film is present only inside the contact holes not existing on the insulating film. The etching composition includes at least one oxidant selected from the group comprising H.sub.2 O.sub.2, O.sub.2, IO.sub.4.sup.-, BrO.sub.3, ClO.sub.3, S.sub.2 O.sub.8.sup.-, KlO.sub.3, H.sub.5 IO.sub.6, KOH, and HNO.sub.3, at least one enhancer selected from the group comprising HF, NH.sub.4 OH, H.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: October 31, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-hwan Kwag, Se-jong Ko, Kyung-seuk Hwang, Jun-ing Gil, Sang-o Park, Dae-hoon Kim, Sang-moon Chon, Ho-Kyoon Chung