Patents by Inventor Dae-Hun Choi

Dae-Hun Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230262980
    Abstract: Disclosed are a three-dimensional semiconductor memory device, a method of fabricating the same, and an electronic system including the same. The semiconductor memory device may include a substrate including a first region and a second region, a plurality of stacks including first and second stacks, each of which includes interlayer insulating layers and gate electrodes stacked alternately with the interlayer insulating layers on the substrate and has a stepped structure on the second region, an insulating layer on stepped structure of the first stack, a plurality of vertical channel structures provided on the first region to penetrate the first stack, and a separation structure separating the first and second stacks from each other. The insulating layer may include one or more dopants, and a dopant concentration of the insulating layer may decrease as a distance from the substrate increases.
    Type: Application
    Filed: September 29, 2022
    Publication date: August 17, 2023
    Inventors: Seungjae Sim, Byung-Sun Park, Jaechul Lee, Dae-Hun Choi
  • Publication number: 20230240072
    Abstract: A non-volatile memory device includes a substrate having a cell array region and an extension region. A mold structure includes a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate such that the mold structure has a step shape that steps downwardly in the extension region in a direction away from the cell array region. A channel structure penetrates through the mold structure in the cell array region, and a cell contact structure penetrates through the mold structure in the extension region. A portion of the cell contact structure is in contact with a portion of an uppermost one of the gate electrodes. The cell contact structure includes a first portion in contact with a side surface of the uppermost one of the gate electrodes and a second portion in contact with a top surface of the uppermost one of the gate electrodes. A width of the first portion is smaller than a width of the second portion.
    Type: Application
    Filed: September 9, 2022
    Publication date: July 27, 2023
    Inventors: Dae-Hun CHOI, Jae Chul LEE, Byung-Sun PARK, Seung Jae SIM
  • Patent number: 11018045
    Abstract: A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Youn Seo, Byung Sun Park, Sung Jin Park, Ji Woon Im, Hyun Seok Lim, Byung Ho Chun, Yu Seon Kang, Hyuk Ho Kwon, Tae Yong Eom, Dae Hun Choi, Dong Hyeop Ha
  • Publication number: 20190148211
    Abstract: A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.
    Type: Application
    Filed: May 31, 2018
    Publication date: May 16, 2019
    Inventors: Ji Youn SEO, Byung Sun PARK, Sung Jin PARK, Ji Woon IM, Hyun Seok LIM, Byung Ho CHUN, Yu Seon KANG, Hyuk Ho KWON, Tae Yong EOM, Dae Hun CHOI, Dong Hyeop HA
  • Patent number: 9312270
    Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: April 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Tae Jang, Myoungbum Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yup Lee, Dae-Hun Choi
  • Patent number: 9040378
    Abstract: Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-Young Lee, Jong-Wan Choi, Dae-Hun Choi, Myoung-Bum Lee
  • Publication number: 20150126007
    Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: Kyung-Tae Jang, Myoungbum Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yup Lee, Dae-Hun Choi
  • Publication number: 20150064885
    Abstract: Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.
    Type: Application
    Filed: June 19, 2014
    Publication date: March 5, 2015
    Inventors: Bo-Young Lee, Jong-Wan Choi, Dae-Hun Choi, Myoung-Bum Lee
  • Publication number: 20120064682
    Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 15, 2012
    Inventors: Kyung-Tae Jang, Myoung Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yuo Lee, Dae-Hun Choi