Patents by Inventor Dae Hwan YUN

Dae Hwan YUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220254805
    Abstract: A semiconductor memory device may include a core pillar extended in a vertical direction, a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering the other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar.
    Type: Application
    Filed: June 29, 2021
    Publication date: August 11, 2022
    Applicant: SK hynix Inc.
    Inventors: Yu Jeong LEE, Dae Hwan YUN, Gil Bok CHOI
  • Publication number: 20220254806
    Abstract: A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming an opening passing through the stack, forming a memory layer in the opening, forming a slit passing through the stack and exposing the first material layers and the second material layers, and forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers.
    Type: Application
    Filed: July 12, 2021
    Publication date: August 11, 2022
    Applicant: SK hynix Inc.
    Inventors: Moon Sik SEO, Dae Hwan YUN
  • Publication number: 20220216231
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.
    Type: Application
    Filed: July 15, 2021
    Publication date: July 7, 2022
    Applicant: SK hynix Inc.
    Inventors: Sungmook LIM, Dae Hwan YUN, Gil Bok CHOI, Jae Hyeon SHIN, In Gon YANG, Hyung Jin CHOI
  • Publication number: 20220208246
    Abstract: The present disclosure relates to an electronic device. A memory device according to the present disclosure includes a memory block coupled to a plurality of local word lines, a peripheral circuit configured to couple the plurality of local word lines to a plurality of global word lines and configured to perform an operation on the memory block, and a control logic configured to control the peripheral circuit to cause or increase a leakage current of the pass switch circuit to discharge potential levels of the plurality of local word lines when the memory device enters a ready state after the operation.
    Type: Application
    Filed: June 30, 2021
    Publication date: June 30, 2022
    Applicant: SK hynix Inc.
    Inventors: Gil Bok CHOI, Dae Hwan YUN
  • Patent number: 11361828
    Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Dae Hwan Yun, Myeong Won Lee
  • Publication number: 20220172780
    Abstract: A memory device, and a method of operating the same, includes a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines. The memory device further includes control logic configured to control the peripheral circuit apply a turn-on voltage to a block word line coupled to the selected word line when the sensing operation is terminated and when potentials of the plurality of word lines are increased due to a recovery operation for channels of the plurality of memory cells after the plurality of word lines have been discharged.
    Type: Application
    Filed: May 5, 2021
    Publication date: June 2, 2022
    Applicant: SK hynix Inc.
    Inventors: Gil Bok CHOI, Dae Hwan YUN
  • Publication number: 20220123113
    Abstract: The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.
    Type: Application
    Filed: April 15, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: Dae Hwan YUN, Gil Bok CHOI
  • Publication number: 20220102371
    Abstract: The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.
    Type: Application
    Filed: March 24, 2021
    Publication date: March 31, 2022
    Applicant: SK hynix Inc.
    Inventors: Dae Hwan YUN, Gil Bok CHOI
  • Publication number: 20200194081
    Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.
    Type: Application
    Filed: February 21, 2020
    Publication date: June 18, 2020
    Inventors: Dae Hwan YUN, Myeong Won LEE
  • Patent number: 10600486
    Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 24, 2020
    Assignee: SK hynix Inc
    Inventors: Dae Hwan Yun, Myeong Won Lee
  • Publication number: 20180294034
    Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.
    Type: Application
    Filed: October 31, 2017
    Publication date: October 11, 2018
    Inventors: Dae Hwan YUN, Myeong Won LEE