Patents by Inventor DaeHyeok Ha

DaeHyeok Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230275013
    Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate in an offset pattern. An electrical component is disposed in a die attach area over a first surface of the substrate. The conductive vias are formed around the die attach area of the substrate. A first conductive layer is formed over the first surface of the substrate, and a second conductive layer is formed over the second surface. An encapsulant is deposited over the substrate and electrical component. The substrate is singulated through the conductive vias. A first conductive via has a greater exposed surface area than a second conductive via. A shielding layer is formed over the electrical component and in contact with a side surface of the conductive vias. The shielding layer may extend over a second surface of substrate opposite the first surface of the substrate.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 31, 2023
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: SungSoo Kim, DaeHyeok Ha, SangMi Park
  • Patent number: 11342294
    Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: May 24, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, OhHan Kim, HeeSoo Lee, DaeHyeok Ha, Wanil Lee
  • Publication number: 20200219835
    Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.
    Type: Application
    Filed: March 17, 2020
    Publication date: July 9, 2020
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, OhHan Kim, HeeSoo Lee, DaeHyeok Ha, Wanil Lee
  • Patent number: 10636756
    Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: April 28, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, OhHan Kim, HeeSoo Lee, DaeHyeok Ha, Wanil Lee
  • Publication number: 20200013738
    Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.
    Type: Application
    Filed: July 5, 2018
    Publication date: January 9, 2020
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, OhHan Kim, HeeSoo Lee, DaeHyeok Ha, Wanil Lee
  • Publication number: 20190318984
    Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate in an offset pattern. An electrical component is disposed in a die attach area over a first surface of the substrate. The conductive vias are formed around the die attach area of the substrate. A first conductive layer is formed over the first surface of the substrate, and a second conductive layer is formed over the second surface. An encapsulant is deposited over the substrate and electrical component. The substrate is singulated through the conductive vias. A first conductive via has a greater exposed surface area than a second conductive via. A shielding layer is formed over the electrical component and in contact with a side surface of the conductive vias. The shielding layer may extend over a second surface of substrate opposite the first surface of the substrate.
    Type: Application
    Filed: April 17, 2018
    Publication date: October 17, 2019
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: SungSoo Kim, DaeHyeok Ha, SangMi Park