Abstract: According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

Abstract: A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

Abstract: A frequency modulation (FM) transmitter, a broadcast receiver having the same, and a method of transmitting an audio are provided. The FM transmitter selects a specific frequency from among frequencies in FM frequency band, which exclude a frequency in use, and transmits an audio signal over the selected specific frequency. Accordingly, the FM transmitter can transmit the audio signal using the confusion-free or interference-free frequency. As a result, a user can select a frequency to transmit the audio of the broadcast receiver easily.

Abstract: A common voltage driving circuit of a liquid crystal display, includes: a clock signal input unit that comprises a plurality of transistors and inputs first and second clock signals according to a gate output voltage; an output node voltage controller that comprises a plurality of transistors and condensers and changes voltages of positive and negative polarity output nodes by the first and second clock signals and first to third gate output voltages; an initialization voltage supply unit that comprises a plurality of transistors and supplies an initialization voltage of the output node voltage controller; and a common voltage output unit that comprises a plurality of transistors and a single condenser and prevents the voltages of the positive and negative polarity output nodes from being changed by using the condenser in alternately outputting higher and lower common voltages according to the voltages of the positive and negative polarity output nodes.

Abstract: A mother glass for a liquid crystal display and a method of fabricating a liquid crystal display using the same are disclosed. The mother glass includes a plurality of cell areas where a plurality of thin films is formed on a substrate, a dummy area disposed outside the plurality of cell areas on the substrate, and a passivation layer. The passivation layer is coated on substantially an overall portion of the plurality of cell areas, and formed in a straight line-like band form along a transverse direction in the dummy area to isolate the cell areas from each other in a longitudinal direction.

Abstract: Disclosed is a control method of an image processing apparatus, the control method including: processing one among a first image, a second image formed on the basis of a different frame rate from that of the first image, and an overlay image where the first image is overlapped with the second image, which is inputted, to be displayable; and compensating for a motion of the processed image on the basis of the first image if it is determined that the inputted image is the first image or the overlay image.

Abstract: A self-align patterning method for forming patterns includes forming a first layer on a substrate, forming a plurality of first hard mask patterns on the first layer, forming a sacrificial layer on top surfaces and sidewalls of the first hard mask patterns, thereby forming a gap between respective facing portions of the sacrificial layer on the sidewalls of the first hard mask patterns, forming a second hard mask pattern in the gap, etching the sacrificial layer using the second hard mask pattern as a mask to expose the first hard mask patterns, exposing the first layer using the exposed first hard mask patterns and the second hard mask pattern, and etching the exposed first layer using the first and second hard mask patterns.

Abstract: A display apparatus and a control method thereof are provided. The apparatus includes a display unit, a signal processing unit, a mode setting unit which sets an environmental mode to one of an exhibition mode and a general mode, and a control unit which determines whether the set environmental mode is the exhibition mode and controls the signal processing unit to reproduce a predetermined advertisement contents and the display unit to display the reproduced advertisement contents if the environmental mode is the exhibition mode. It is possible to provide an advertisement contents using the display apparatus and the control method thereof.

Abstract: A display apparatus includes a display unit, a storage unit which stores a zone name and standard time information corresponding to the zone name, a user interface (UI) generator which generates a time information image, and a controller which receives local real-time information from an external source, calculates a time corresponding to a selected zone based on the local real-time information and the standard time information, and controls the UI generator to generate the time information image containing the calculated time to be displayed on the display unit.

Abstract: A crystal liquid display and a method of manufacturing the same are disclosed. The liquid crystal display includes upper and lower substrates facing each other, a thin film transistor, a pixel electrode, and a passivation layer. The thin film transistor is provided at an intersection of a gate line and a data line on the lower substrate, and the gate line and the data line cross at right angles. The pixel electrode is provided in a pixel area defined by the gate line and the data line. The passivation layer covers the entire surface of the lower substrate, and includes an opening having an elevation difference surface on a predetermined portion thereof. A concave-convex pattern is provided along the elevation difference surface of the opening.

Abstract: A common voltage driving circuit of a liquid crystal display, includes: a clock signal input unit that comprises a plurality of transistors and inputs first and second clock signals according to a gate output voltage; an output node voltage controller that comprises a plurality of transistors and condensers and changes voltages of positive and negative polarity output nodes by the first and second clock signals and first to third gate output voltages; an initialization voltage supply unit that comprises a plurality of transistors and supplies an initialization voltage of the output node voltage controller; and a common voltage output unit that comprises a plurality of transistors and a single condenser and prevents the voltages of the positive and negative polarity output nodes from being changed by using the condenser in alternately outputting higher and lower common voltages according to the voltages of the positive and negative polarity output nodes.

Abstract: Example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device. Other example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device without a generation of a bridge between adjacent metal wirings. In a method of forming a metal wiring in a semiconductor device, at least one metal layer and at least one barrier layer may be sequentially formed on a substrate. A metal blocking layer may be formed on the at least one barrier metal layer. A hard mask layer may be formed on the metal blocking layer. A hard mask pattern may be formed on the metal blocking layer by etching the hard mask layer without an exposure of the at least one barrier metal layer. A metal blocking layer pattern may be formed on the at least one barrier metal layer by etching the metal blocking layer using the hard mask pattern as an etching mask.

Abstract: A non-volatile memory device includes a substrate that is divided into a field region and an active region by isolation layer patterns. The active region has an active trench for increasing an effective area of the active region. A tunnel oxide layer is formed on the active region. A floating gate pattern is formed on the tunnel oxide layer to fill up the active trench. A dielectric layer pattern is formed on the floating gate pattern. A control gate pattern is formed on the dielectric layer pattern. Thus, the non-volatile memory device has an increased effective area of the active region so that the non-volatile memory device may have improved operational characteristics.

Abstract: Methods of forming non-volatile memory devices include forming a device isolation layer and a gate pattern of a non-volatile memory cell transistor, on a semiconductor substrate. This gate pattern includes a floating gate electrode and a control gate line that extends on the floating gate electrode and on the device isolation layer. At least a first portion of a first sidewall of the gate pattern is then covered with a first mask that exposes upper corners of the control gate line. The device isolation layer is then selectively etched at a first rate to define an at least partial opening therein. During this etching step, the upper corners of the control gate line are also etched back at a second rate less than the first rate.

Abstract: A self-align patterning method for forming patterns includes forming a first layer on a substrate, forming a plurality of first hard mask patterns on the first layer, forming a sacrificial layer on top surfaces and sidewalls of the first hard mask patterns, thereby forming a gap between respective facing portions of the sacrificial layer on the sidewalls of the first hard mask patterns, forming a second hard mask pattern in the gap, etching the sacrificial layer using the second hard mask pattern as a mask to expose the first hard mask patterns, exposing the first layer using the exposed first hard mask patterns and the second hard mask pattern, and etching the exposed first layer using the first and second hard mask patterns.

Abstract: A mother glass for a liquid crystal display and a method of fabricating a liquid crystal display using the same are disclosed. The mother glass includes a plurality of cell areas where a plurality of thin films is formed on a substrate, a dummy area disposed outside the plurality of cell areas on the substrate, and a passivation layer. The passivation layer is coated on substantially an overall portion of the plurality of cell areas, and formed in a straight line-like band form along a transverse direction in the dummy area to isolate the cell areas from each other in a longitudinal direction.

Abstract: Example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device. Other example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device without a generation of a bridge between adjacent metal wirings. In a method of forming a metal wiring in a semiconductor device, at least one metal layer and at least one barrier layer may be sequentially formed on a substrate. A metal blocking layer may be formed on the at least one barrier metal layer. A hard mask layer may be formed on the metal blocking layer. A hard mask pattern may be formed on the metal blocking layer by etching the hard mask layer without an exposure of the at least one barrier metal layer. A metal blocking layer pattern may be formed on the at least one barrier metal layer by etching the metal blocking layer using the hard mask pattern as an etching mask.

Abstract: In a method of manufacturing a non-volatile semiconductor memory device that includes a first region having a first gate structure and a second region having a second gate structure, the first gate structure may include a tunnel oxide layer pattern, a first conductive layer pattern, a dielectric layer pattern and a second conductive layer pattern. A first photoresist pattern may be formed on the second conductive layer pattern to form a source line which may be formed in a region of the first area by implanting impurities. A second photoresist pattern may be formed on a hard mask layer in the second region of the substrate to form a hard mask pattern on a third conductive layer. The second gate structure having substantially vertical sidewalls may be formed in the second area by etching the third conductive layer using the hard mask pattern.

Abstract: A non-volatile memory device includes a substrate that is divided into a field region and an active region by isolation layer patterns. The active region has an active trench for increasing an effective area of the active region. A tunnel oxide layer is formed on the active region. A floating gate pattern is formed on the tunnel oxide layer to fill up the active trench. A dielectric layer pattern is formed on the floating gate pattern. A control gate pattern is formed on the dielectric layer pattern. Thus, the non-volatile memory device has an increased effective area of the active region so that the non-volatile memory device may have improved operational characteristics.

Abstract: An image display apparatus capable of analog/digital tuning by a DTV tuner and an analog/digital tuning method thereof are provided. The image display apparatus includes a digital television (DTV) tuner for tuning at least one of an analog signal and a digital signal, a bus switch for switching the DTV tuner to tune at least one of an analog signal and a digital signal, and a control unit for controlling an operation of the bus switch in accordance with at least one mode selected between an analog mode and a digital mode whereby the analog tuning is implemented with a single DTV tuner, so that not only a cost of the analog tuner is reduced but also the design efficiency is increased due to increased space utilization.