Abstract: Disclosed is a memory device which a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, in which an erase operation is to be performed, and control logic configured to control the memory cell array and the voltage generator. The voltage generator is configured to provide the erase voltage to at least one of a bit line and a common source line connected with the target block and to provide the row line voltages to row lines connected with the target block, and the control logic is configured to change a slope of the erase voltage and a floating time of at least one row line among the row lines depending on a program/erase cycle.

Abstract: A duplexing system and method for writing a back-up list in which a back-up process is substituted for a process having an error while performing plural processes. Memory space to store a back-up order list is allotted to two bytes per process. A number of the leading order process is stored in the first byte, whereas a number of following order process is stored in the second byte. Further, the top priority bit or the last bit of each byte of memory space in which the process to be backed-up is allotted is set, and thus the existence of a registration is displayed. Further, if error an occurs at plural processes, a non back-up process generates a back-up order list according to time sequence of error generation. If an error occurs at a process of another top priority order while operating a back-up of a back-up process, the process is registered at the leading order list.