Abstract: Disclosed herein are an apparatus and method for processing vehicle data security based on a cloud.

Abstract: An encoding/decoding apparatus and method for controlling a channel signal is disclosed, wherein the encoding apparatus may include an encoder to encode an object signal, a channel signal, and rendering information for the channel signal, and a bit stream generator to generate, as a bit stream, the encoded object signal, the encoded channel signal, and the encoded rendering information for the channel signal.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: The memory device includes a content addressable memory (CAM) block including a plurality of pages, peripheral circuits configured to perform a CAM data read operation to read a CAM data comprising a plurality of check data each indicating whether bad block information is included in a region of the CAM data from a page sequentially selected among the plurality of pages, a CAM data read controller configured to perform a CAM data load operation to receive the CAM data from the peripheral circuits and output the CAM data to an external memory controller, and stop the CAM data load operation based on at least one check data among the plurality of check data included in the CAM data.

Abstract: The present technology relates to a memory device, a memory system including the same, and a method of operating the memory system. The memory device includes a cam block including a plurality of pages, peripheral circuits configured to read a cam data of a page unit that is stored in a selected page among the plurality of pages of the cam block during a cam data read operation, a cam data read controller configured to receive the read cam data of the page unit from the peripheral circuits during a cam data load operation and configured to output the received cam data of the page unit as output cam data, and a control logic configured to control the peripheral circuits to perform the cam data read operation and the cam data load operation. The cam data read controller stops the cam data load operation based on a check data that is included in the read cam data of the page unit.

Abstract: A semiconductor memory device includes a column address generation circuit suitable for generating contents addressable memory (CAM) column addresses for duplicated CAM data, a column selection circuit suitable for allocating columns to the duplicated CAM data according to the CAM column addresses, and a plurality of page buffer units, each unit being coupled to a corresponding memory group through the allocated columns, and suitable for storing the duplicated CAM data in the memory groups through the allocated columns. The allocated columns are of arranged sequentially within each memory group in a circular order, and a part of the CAM column addresses represent columns which are physically apart by a predetermined number of columns within a memory group.

Abstract: A nonvolatile memory device includes a plurality of global word lines, a voltage pump configured to generate a plurality of voltages, a control unit configured to divide the plurality of global word lines into a first group and a second group in response to an input row address and generate control signals, a first selection unit configured to output at least two different voltages that are to be applied to global word lines of the first group, a second selection unit configured to output a voltage that is to be applied to global word lines of the second group, and a third selection unit configured to apply output voltages of the first selection unit to the global word lines of the first group, and apply an output voltage of the second selection unit to the global word lines of the second group.

Abstract: A semiconductor memory device includes a random address generation unit configured to receive a multi-bit source address and generate a multi-bit random address and a signal mixing unit configured to mix the multi-bit random address with a data, wherein the random address generation unit has a plurality of transmission lines configured to electrically connect the plurality of input terminals respectively corresponding to bits of the source address and the plurality of output terminals respectively corresponding to bits of the random address in one-to-one correspondence regardless of an order of the bits of the source address.

Abstract: An integrated circuit includes a random address generation unit configured to generate a first random address for a data randomizing operation, an address conversion unit configured to convert the first random address and generate a second random address, and a synchronization output unit configured to sequentially output the first and second random addresses in synchronization with a clock signal.

Abstract: An integrated circuit includes a random address generation unit configured to generate a first random address for a data randomizing operation, an address conversion unit configured to convert the first random address and generate a second random address, and a synchronization output unit configured to sequentially output the first and second random addresses in synchronization with a clock signal.

Abstract: A semiconductor memory device includes a random address generation unit configured to receive a multi-bit source address and generate a multi-bit random address and a signal mixing unit configured to mix the multi-bit random address with a data, wherein the random address generation unit has a plurality of transmission lines configured to electrically connect the plurality of input terminals respectively corresponding to bits of the source address and the plurality of output terminals respectively corresponding to bits of the random address in one-to-one correspondence regardless of an order of the bits of the source address.

Abstract: A nonvolatile memory device includes a plurality of global word lines, a voltage pump configured to generate a plurality of voltages, a control unit configured to divide the plurality of global word lines into a first group and a second group in response to an input row address and generate control signals, a first selection unit configured to output at least two different voltages that are to be applied to global word lines of the first group, a second selection unit configured to output a voltage that is to be applied to global word lines of the second group, and a third selection unit configured to apply output voltages of the first selection unit to the global word lines of the first group, and apply an output voltage of the second selection unit to the global word lines of the second group.