Abstract: A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three foactors in increasing the effective areas for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterned to selectively remove the storage poly layer, and the spacer makes the storage poly to be remained maximize or be proper by controlling the size thereof; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plate poly material is coated and wraps.

Abstract: A distributed control circuit for a sense amplifier is provided in which each sense amplifier has a pair of sensing control transistors connected in serial with each sensing node of the sense amplifiers. Each gate of the sensing control transistors has a respective resistor connected in sequence from the gate of the uppermost sensing control transistor to the gate of the lowermost sensing transistor. A delay compensation resistor is connected by the unit of a sensing control transistor group having the number of the sensing control transistors as many as an integer k.