Abstract: The present disclosure includes cationic carrier units comprising (i) a water-soluble polymer, (ii) a positively charged carrier, (iii) a hydrophobic moiety, and (iv) a crosslinking moiety, wherein when the cationic carrier unit is mixed with an anionic payload (e.g., an antisense oligonucleotide) that electrostatically interacts with the cationic carrier unit, the resulting composition self-organizes into a micelle encapsulating the anionic payload in its core. The cationic carrier units can also comprise a tissue specific targeting moiety, which would be displayed on the surface of the micelle. The disclosure also includes micelles comprising the cationic carrier units of the disclosure, methods of manufacture of cationic carrier units and micelles, pharmaceutical compositions comprising the micelles, and also methods of treating diseases or conditions comprising administering the micelles to a subject in need thereof.

Abstract: A display device includes a substrate, conductive pads arranged on the substrate over a plurality of rows, and a drive circuit chip including bumps arranged over a plurality of rows to be electrically connected with the conductive pads, and the conductive pads arranged in a same row are arranged in parallel, and the bumps arranged in a same row are arranged in a zigzag form so as to be partially shifted.

Abstract: The present disclosure relates to a DC-DC converter, a vehicle, and a control method including the same, and more particularly, to a DC-DC converter, a vehicle, and a control method including the same capable of effectively detecting and responding to an interlock failure of a connector.

Abstract: The present disclosure includes cationic carrier units comprising (i) a water soluble polymer, (ii) a positively charged carrier, (iii) a hydrophobic moiety, and (iv) a crosslinking moeity, wherein when the cationic carrier unit is mixed with an anionic payload (e.g., an RNA and/or DNA) that electrostatically interacts with the cationic carrier unit, the resulting composition self-organizes into a micelle encapsulating the anionic payload in its core. The cationic carrier units can also comprise a tissue specific targeting moiety, which would be displayed on the surface of the micelle. The disclosure also includes micelles comprising the cationic carrier units of the disclosure, methods of manufacture of cationic carrier units and micelles, pharmaceutical compositions comprising the micelles, and also methods of treating diseases or conditions comprising administering the micelles to a subject in need thereof.

Abstract: In one example, an electronic device includes an embedded module, which includes a module substrate and module components coupled to the module substrate. A device substrate is coupled to the first module substrate. Device terminals are coupled to the module components and a device encapsulant structure encapsulates the embedded module, the device substrate, and the device terminals. A portion of the device substrate is exposed from the device encapsulant structure and portions of the device terminals are exposed from the device encapsulant structure. Other examples and related methods are also disclosed herein.

Abstract: Proposed is a substrate heating unit including: a laser generator providing a laser beam for heating a substrate; and a beam shaper processing the laser beam from the laser generator and selectively providing one of a first beam having a uniform energy distribution and a second beam having an edge-enhanced energy distribution to the substrate.

Abstract: A multilayer ceramic electronic component includes: a body including dielectric layers as well as a plurality of internal electrodes stacked with respective dielectric layers interposed therebetween and including a first metal; and external electrodes disposed on external surfaces of the body including a second metal, wherein at least some of the plurality of internal electrodes include a core-shell region including the first and second metals, and average contents of the second metal in a core portion and a shell portion of the core-shell region are different from each other.

Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.

Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.

Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.

Abstract: Disclosed is a bio illuminance measuring apparatus including a circadian lambda filter passing external light along according to a circadian rhythm sensitivity curve, a visual lambda filter passing the external light along according to a visual sensitivity curve, a photo sensing portion sensing and converting the external light, which has passed through the circadian lambda filter, into a circadian wavelength signal and sensing and converting the external light, which has passed through the visual lambda filter, into a visual wavelength signal, and an illuminance calculating portion which calculates a ratio between the circadian wavelength signal and the visual wavelength signal, calculates a circadian action factor by applying the ratio between the circadian wavelength signal and the visual wavelength signal to a circadian action function which varies according to the visual wavelength signal, and calculates a bio illuminance value of the external light on the basis of the circadian action factor.

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

Abstract: Disclosed are an apparatus and a system for managing circadian rhythm. The apparatus includes an illuminance measuring portion which measures a bio illuminance value of external light using a circadian lambda filter which passes the external light along according to a circadian rhythm sensitivity curve and a visual lambda filter which passes the external light along according to a visual sensitivity curve, a controller which outputs a control signal for reinforcing a user's circadian rhythm on the basis of the bio illuminance value, and a circadian rhythm reinforcing portion which emits light of a circadian wavelength band toward the user according to the control signal.

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.