Patents by Inventor Dae-Jin Kwon
Dae-Jin Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240109397Abstract: A method for controlling an electric heater of a vehicular heating, ventilation, and air conditioning (HVAC) system includes turning on the electric heater; determining whether an ambient air temperature of a vehicle is higher than or equal to a threshold ambient air temperature, and a battery temperature is lower than or equal to a threshold battery temperature; determining whether battery efficiency is lower than or equal to threshold efficiency when the ambient air temperature of the vehicle is higher than or equal to the threshold ambient air temperature, and the battery temperature is lower than or equal to the threshold battery temperature; and turning off the electric heater when the battery efficiency is lower than or equal to the threshold efficiency, wherein the electric heater is configured to receive electric energy from the battery.Type: ApplicationFiled: March 30, 2023Publication date: April 4, 2024Inventors: Dae Hyun Song, Chang Gi Ryu, Woo Jin Lee, Dong Ju Ko, Hyun Hun Choi, Chun Kyu Kwon, In Uk Ko
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Patent number: 10303931Abstract: An apparatus is for irradiating light for obtaining a face image of an authentication target. The apparatus includes a first light source unit having a first glancing angle, a second light source unit having a second glancing angle greater than the first glancing angle, and an external light information acquisition unit configured to acquire environment information on an external light other than the first light source unit and the second light source unit for the authentication target. The apparatus further includes a control unit configured to determine a power ratio of a second driving power supplied to the second light source unit to a first driving power supplied to the first light source unit based on the environment information and control currents to be supplied to the first light source unit and the second light source unit based on the power ratio.Type: GrantFiled: June 26, 2017Date of Patent: May 28, 2019Assignee: SUPREMA INC.Inventors: Hochul Shin, Kideok Lee, Dae Jin Kwon, Hyun Suk Lee, Bong Seop Song, Jae Won Lee
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Patent number: 10128254Abstract: A semiconductor device includes a substrate, a first pattern, a first gate electrode, and a second pattern. The first pattern is disposed on the substrate and extends in a first direction substantially vertical to an upper surface of the substrate, and includes a first part, a second part and a third part sequentially disposed on the substrate. The first gate electrode is connected to the second part and extends in a second direction different from the first direction. The second pattern is disposed on the substrate, extends in the first direction, is connected to the first part, and does not contact the first gate electrode.Type: GrantFiled: June 20, 2016Date of Patent: November 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Jin Kwon, Kang-Ill Seo
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Publication number: 20180173941Abstract: An apparatus is for irradiating light for obtaining a face image of an authentication target. The apparatus includes a first light source unit having a first glancing angle, a second light source unit having a second glancing angle greater than the first glancing angle, and an external light information acquisition unit configured to acquire environment information on an external light other than the first light source unit and the second light source unit for the authentication target. The apparatus further includes a control unit configured to determine a power ratio of a second driving power supplied to the second light source unit to a first driving power supplied to the first light source unit based on the environment information and control currents to be supplied to the first light source unit and the second light source unit based on the power ratio.Type: ApplicationFiled: June 26, 2017Publication date: June 21, 2018Applicant: SUPREMA INC.Inventors: Hochul SHIN, Kideok LEE, Dae Jin KWON, Hyun Suk LEE, Bong Seop SONG, Jae Won LEE
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Patent number: 9875791Abstract: Provided are a semiconductor device. The semiconductor device includes an SRAM cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal with the first read buffer transistor, wherein the first read buffer transistor includes a first channel pattern extending in a first direction vertical to an upper surface of the substrate, a first gate electrode which covers a part of the first channel pattern, and a first drain pattern which does not contact the first gate electrode, and which extends in the first direction, and which is connected to the first channel pattern.Type: GrantFiled: July 31, 2017Date of Patent: January 23, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Jin Kwon, Kang-Ill Seo
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Publication number: 20170365611Abstract: A semiconductor device includes a substrate, a first pattern, a first gate electrode, and a second pattern. The first pattern is disposed on the substrate and extends in a first direction substantially vertical to an upper surface of the substrate, and includes a first part, a second part and a third part sequentially disposed on the substrate. The first gate electrode is connected to the second part and extends in a second direction different from the first direction. The second pattern is disposed on the substrate, extends in the first direction, is connected to the first part, and does not contact the first gate electrode.Type: ApplicationFiled: June 20, 2016Publication date: December 21, 2017Inventors: DAE-JIN KWON, KANG-ILL SEO
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Publication number: 20170330614Abstract: Provided are a semiconductor device. The semiconductor device includes an SRAM cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal with the first read buffer transistor, wherein the first read buffer transistor includes a first channel pattern extending in a first direction vertical to an upper surface of the substrate, a first gate electrode which covers a part of the first channel pattern, and a first drain pattern which does not contact the first gate electrode, and which extends in the first direction, and which is connected to the first channel pattern.Type: ApplicationFiled: July 31, 2017Publication date: November 16, 2017Inventors: DAE-JIN KWON, KANG-ILL SEO
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Patent number: 9754660Abstract: Provided are a semiconductor device. The semiconductor device includes an SRAM cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal with the first read buffer transistor, wherein the first read buffer transistor includes a first channel pattern extending in a first direction vertical to an upper surface of the substrate, a first gate electrode which covers a part of the first channel pattern, and a first drain pattern which does not contact the first gate electrode, and which extends in the first direction, and which is electrically connected to the first channel pattern.Type: GrantFiled: November 19, 2015Date of Patent: September 5, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Jin Kwon, Kang-Ill Seo
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Patent number: 9702041Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: GrantFiled: June 8, 2016Date of Patent: July 11, 2017Assignees: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
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Publication number: 20170148505Abstract: Provided are a semiconductor device. The semiconductor device includes an SRAM cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal with the first read buffer transistor, wherein the first read buffer transistor includes a first channel pattern extending in a first direction vertical to an upper surface of the substrate, a first gate electrode which covers a part of the first channel pattern, and a first drain pattern which does not contact the first gate electrode, and which extends in the first direction, and which is electrically connected to the first channel pattern.Type: ApplicationFiled: November 19, 2015Publication date: May 25, 2017Inventors: DAE-JIN KWON, Kang-Ill Seo
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Publication number: 20160281234Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: ApplicationFiled: June 8, 2016Publication date: September 29, 2016Applicants: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun WON, Yong-min YOO, Dae-youn KIM, Young-hoon KIM, Dae-jin KWON, Weon-hong KIM
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Patent number: 9406502Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: GrantFiled: April 14, 2015Date of Patent: August 2, 2016Assignees: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
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Publication number: 20150221497Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: ApplicationFiled: April 14, 2015Publication date: August 6, 2015Applicants: GENITECH, INC., SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-jun WON, Yong-min YOO, Dae-youn KIM, Young-hoon KIM, Dae-jin KWON, Weon-hong KIM
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Patent number: 9029244Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: GrantFiled: September 21, 2012Date of Patent: May 12, 2015Assignees: Samsung Electronics Co., Ltd., Genitech, Inc.Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
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Publication number: 20120052829Abstract: A terminal and a network connection method to automatically connect devices to a network and transfer data to the devices using the received signal strength indication (RSSI) levels of signals respectively received from the devices. The terminal may transfer different data to devices based on the RSSI level of the signals received from the devices and/or the locations of the devices.Type: ApplicationFiled: August 1, 2011Publication date: March 1, 2012Applicant: PANTECH CO., LTD.Inventors: In Youl LEE, Dae Jin KWON, Min Su KIM, Chang Hyun KIM, Joong Hyun LEE, Tae Hoon LEE
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Publication number: 20110097905Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: ApplicationFiled: December 29, 2010Publication date: April 28, 2011Applicants: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
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Patent number: 7888772Abstract: A semiconductor device includes a fuse transistor for fuse programming and a fuse block connected to the fuse transistor, wherein the fuse block comprises a fuse line and a heat spreading structure connected to the fuse line. The electrical fuse employs the heat spreading structure connected to the fuse line to prevent a rupture of the electrical fuse such that heat, which is generated in the fuse line during a blowing of the fuse line, is spread throughout the heat spreading structure. Thus, a sensing margin of the electrical fuse can be secured and a deterioration of devices adjacent to the electrical fuse by heat generated in the electrical fuse can be prevented.Type: GrantFiled: January 11, 2008Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Jin Kwon, Woo-Sik Kim, Maeda Shigenobu, Seung-Hwan Lee, Sung-Rey Wi, Wang-Xiao Quan, Hyun-Min Choi
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Patent number: 7833580Abstract: A method of forming a carbon nano-material layer may involve a cyclic deposition technique. In the method, a chemisorption layer or a chemical vapor deposition layer may be formed on a substrate. Impurities may be removed from the chemisorption layer or the chemical vapor deposition layer to form a carbon atoms layer on the substrate. More than one carbon atoms layer may be formed by repeating the method.Type: GrantFiled: June 3, 2004Date of Patent: November 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Jun Won, Dae-Jin Kwon, Yong-Kuk Jeong
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Patent number: 7732296Abstract: In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corresType: GrantFiled: January 25, 2006Date of Patent: June 8, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-min Park, Seok-jun Won, Min-woo Song, Yong-kuk Jeong, Dae-jin Kwon, Weon-hong Kim
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Patent number: 7679124Abstract: An analog capacitor capable of reducing the influence of an applied voltage on a capacitance and a method of manufacturing the analog capacitor are provided. The analog capacitor includes a lower electrode which is formed on a substrate, a multi-layered dielectric layer which includes at least one oxide layer and at least one oxynitride layer which are formed of a material selected from the group consisting of Hf, Al, Zr, La, Ba, Sr, Ti, Pb, Bi and a combination thereof and is formed on the lower electrode, and an upper electrode which is formed on the multi-layered dielectric layer.Type: GrantFiled: July 22, 2005Date of Patent: March 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-kuk Jeong, Seok-jun Won, Dae-jin Kwon, Min-woo Song, Weon-hong Kim