Patents by Inventor Dae-Kwon Kang
Dae-Kwon Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119949Abstract: An encoding/decoding apparatus and method for controlling a channel signal is disclosed, wherein the encoding apparatus may include an encoder to encode an object signal, a channel signal, and rendering information for the channel signal, and a bit stream generator to generate, as a bit stream, the encoded object signal, the encoded channel signal, and the encoded rendering information for the channel signal.Type: ApplicationFiled: November 30, 2023Publication date: April 11, 2024Applicant: Electronics and Telecommunications Research InstituteInventors: Jeong Il SEO, Seung Kwon BEACK, Dae Young JANG, Kyeong Ok KANG, Tae Jin PARK, Yong Ju LEE, Keun Woo CHOI, Jin Woong KIM
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Patent number: 10216082Abstract: According to example embodiments of inventive concepts, a layout design system includes a processor, a storage unit configured to store a layout design, and a stitch module. The layout design includes a first pattern group and a second pattern group disposed in accordance with a design. The first pattern group including a first pattern for patterning at a first time. The second pattern group including a second pattern for patterning at a second time that is different than the first time. The stitch module is configured to detect an iso-pattern of the second pattern using the processor. The stitch module is configured to repetitively designate at least one of the first pattern, which is spaced apart from the iso-pattern by a pitch or more, to the second pattern group using the processor.Type: GrantFiled: January 20, 2016Date of Patent: February 26, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-kwon Kang, Ji-Young Jung, Dong-Gyun Kim, Jae-Seok Yang, Sung-Keun Park, Young-Gook Park
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Patent number: 9928330Abstract: In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.Type: GrantFiled: June 11, 2015Date of Patent: March 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Kwon Kang, Ji-young Jung, Dong-Gyun Kim, Jae-Seok Yang, Sung-Wook Hwang
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Patent number: 9874810Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.Type: GrantFiled: April 21, 2016Date of Patent: January 23, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Jung, Dae-Kwon Kang, Dong-Gyun Kim, Jae-Seok Yang, Sung-Wook Hwang
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Patent number: 9841672Abstract: A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.Type: GrantFiled: April 17, 2015Date of Patent: December 12, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Kwon Kang, Jae-Seok Yang, Sung-Wook Hwang, Dong-Gyun Kim, Ji-Young Jung
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Patent number: 9836565Abstract: Provided are an electronic design automation apparatus and method. The electronic design automation method includes: loading, by a processor, a rule file having limitations on a reference design file; extracting, by the processor, a plurality of unit operations for respectively performing the limitations from the loaded file; and automatically forming, by the processor, a flowchart corresponding to the rule file based on relations between the plurality of unit operations.Type: GrantFiled: August 12, 2015Date of Patent: December 5, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Dae-Kwon Kang
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Patent number: 9652578Abstract: A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.Type: GrantFiled: March 31, 2015Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Gyun Kim, Sung-Wook Hwang, Dae-Kwon Kang, Jae-Seok Yang, Ji-Young Jung
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Publication number: 20160313638Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.Type: ApplicationFiled: April 21, 2016Publication date: October 27, 2016Inventors: Ji-Young Jung, Dae-Kwon KANG, Dong-Gyun KIM, Jae-Seok YANG, Sung-Wook HWANG
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Publication number: 20160306914Abstract: According to example embodiments of inventive concepts, a layout design system includes a processor, a storage unit configured to store a layout design, and a stitch module. The layout design includes a first pattern group and a second pattern group disposed in accordance with a design. The first pattern group including a first pattern for patterning at a first time. The second pattern group including a second pattern for patterning at a second time that is different than the first time. The stitch module is configured to detect an iso-pattern of the second pattern using the processor. The stitch module is configured to repetitively designate at least one of the first pattern, which is spaced apart from the iso-pattern by a pitch or more, to the second pattern group using the processor.Type: ApplicationFiled: January 20, 2016Publication date: October 20, 2016Inventors: Dae-kwon KANG, Ji-Young JUNG, Dong-Gyun KIM, Jae-Seok YANG, Sung-Keun PARK, Young-Gook PARK
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Publication number: 20160188773Abstract: Provided are an electronic design automation apparatus and method. The electronic design automation method includes: loading, by a processor, a rule file having limitations on a reference design file; extracting, by the processor, a plurality of unit operations for respectively performing the limitations from the loaded file; and automatically forming, by the processor, a flowchart corresponding to the rule file based on relations between the plurality of unit operations.Type: ApplicationFiled: August 12, 2015Publication date: June 30, 2016Inventor: DAE-KWON KANG
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Publication number: 20160070848Abstract: A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.Type: ApplicationFiled: April 17, 2015Publication date: March 10, 2016Inventors: DAE-KWON KANG, JAE-SEOK YANG, SUNG-WOOK HWANG, DONG-GYUN KIM, JI-YOUNG JUNG
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Publication number: 20160070838Abstract: In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.Type: ApplicationFiled: June 11, 2015Publication date: March 10, 2016Inventors: Dae-Kwon KANG, Ji-young JUNG, Dong-Gyun KIM, Jae-Seok YANG, Sung-Wook HWANG
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Publication number: 20160026744Abstract: A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.Type: ApplicationFiled: March 31, 2015Publication date: January 28, 2016Inventors: Dong-Gyun KIM, Sung-Wook HWANG, Dae-Kwon KANG, Jae-Seok YANG, Ji-Young JUNG
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Publication number: 20090014807Abstract: Dual stress liners for CMOS applications are provided. The dual stress liners can be formed from silicon nitride having a first portion for inducing a first stress and a second portion for inducing a second stress. An interface between the first and second stress portions is self-aligned and co-planar. To produce a co-planar self-aligned interface, polishing, for example, mechanical chemical polishing is used.Type: ApplicationFiled: July 13, 2007Publication date: January 15, 2009Applicants: Chartered Semiconductor Manufacturing, Ltd., Samsung Electronics Co., Ltd, International Business Machines Corporation, Infineon Technologies AGInventors: Teck Jung TANG, Dae Kwon Kang, Sunfei Fang, Tae Hoon Lee, Scott D. Allen, Fang Chen, Frank Huebinger, Jun Jung Kim, Jae Eun Park
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Publication number: 20080029823Abstract: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.Type: ApplicationFiled: October 11, 2007Publication date: February 7, 2008Inventors: Jae-Eon Park, Ja-Hum Ku, Jun-Jung Kim, Dae-Kwon Kang, Young Teh
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Patent number: 7297584Abstract: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.Type: GrantFiled: October 7, 2005Date of Patent: November 20, 2007Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd.Inventors: Jae-Eon Park, Ja-Hum Ku, Jun-Jung Kim, Dae-Kwon Kang, Young Way Teh
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Publication number: 20070082439Abstract: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.Type: ApplicationFiled: October 7, 2005Publication date: April 12, 2007Inventors: Jae-Eon Park, Ja-Hum Ku, Jun-Jung Kim, Dae-Kwon Kang, Young Teh