Abstract: Provided is a field effect transistor including a drain region, a source region, and a channel region. The field effect transistor may further include a gate electrode on or surrounding at least a portion of the channel region, and a gate dielectric layer between the channel region and the gate electrode. A portion of the channel region adjacent the source region has a sectional area smaller than that of another portion of the channel region adjacent the drain region.

Abstract: A non-volatile memory apparatus and method of manufacturing the same is disclosed, which uses a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell. The SONOS cell comprises the silicon substrate (S), the dielectric layers of stacked oxide-nitride-oxide (ONO), the gate electrode (S) and the source and drain terminals separated by the gate length. The programming of the cell is done by the injection of channel hot electrons into trap sites in between the oxide and the nitride layer, while erasing is done by discharging those trapped electrons via F-N tunneling. This B/L contacted SONOS cell combines both the inherent advantages of memory operation, free of drain turn-on and over-erase and the ability to harness without modification the existing flash EEPROM technology for mass production.

Abstract: A hot carrier measuring circuit of the present invention, which measures the characteristic degradation of a semiconductor device due to AC operation, includes a pulse generator generating at least two pulse signals which are partially overlapped with each other and have various duty ratios, a level shifter shifting the pulse signal which are generated in the pulse generator to a desired voltage level, and a measuring device receiving the pulse signals outputted from the level shifter to at least one terminal thereof.

Abstract: Sensing circuit for a semiconductor device and a sensing method using the same which allows sensing of a selected nonvolatile memory cell at a low voltage, a low power, and a fast speed, and has a high sensing reliability, the circuit including a bitline connected to a drain terminal of a memory cell through a Y-decoder, a senseline for sensing, and forwarding a data in the memory cell, a switching unit for switching between the bitline and the senseline, a first current supply unit disposed between a power source and the bitline for supplying a current to the bitline to the memory cell, a second current supply unit disposed between the power source and the senseline for supplying a current to the senseline, a voltage level shifter for providing a voltage difference between the bitline and the senseline, and a sense MOS transistor disposed between the senseline and the ground voltage and having a gate terminal connected to one end of the voltage level shifter.

Abstract: A device and method for sensing data in a multi-bit memory cell of a memory cell array unit is provided where each memory cell has at least two threshold voltage levels. The device can include a multistep current source unit to provide quantized voltages, each having a width smaller than a threshold voltage distribution in a selected memory cell, according to a current flowing through the selected memory cell. An analog-to-digital converter compares the quantized voltages from the multistep current source unit with a plurality of reference voltages to provide a state of the memory cell in binary form. The device and method for sensing data in the multi-bit memory cell uses the quantized voltages to increase sensing reliability, increases sensing speed and increases a gap between the quantized voltages relative to the threshold voltage distribution.

Abstract: Flash EEPROM memory devices having mid-channel injection characteristics include a substrate having source and drain regions of first conductivity type therein extending adjacent a surface thereof. A stacked-gate electrode is also provided on the surface, between the source and drain regions. To provide improved mid-channel injection characteristics during programming, a preferred semiconductor channel region is provided in the substrate at a location extending opposite the stacked-gate electrode. This channel region comprises a first "source-side" region of second conductivity type (e.g., P+) and a second "drain-side" region of predetermined conductivity type (e.g., P-, N-). The second region has a lower first conductivity type dopant concentration therein than the drain region and a lower second conductivity type dopant concentration therein than said first region, and more preferably has a lower second conductivity type dopant concentration therein than said substrate.