Patents by Inventor Daero KIM

Daero KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY CONTROLLER PERFORMING DATA TRAINING, SYSTEM-ON-CHIP INCLUDING THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY CONTROLLER
    Publication number: 20240046982
    Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 8, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daero KIM, Kyunghoi Koo, Sujeong Kim, Juyoung Kim, Sanghune Park, Jiyeon Park, Jihun Oh, Kyoungwon Lee
  • Memory controller performing data training, system-on-chip including the memory controller, and operating method of the memory controller
    Patent number: 11830541
    Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: November 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daero Kim, Kyunghoi Koo, Sujeong Kim, Juyoung Kim, Sanghune Park, Jiyeon Park, Jihun Oh, Kyoungwon Lee
  • MEMORY CONTROLLER PERFORMING DATA TRAINING, SYSTEM-ON-CHIP INCLUDING THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY CONTROLLER
    Publication number: 20220392520
    Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.
    Type: Application
    Filed: January 6, 2022
    Publication date: December 8, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daero KIM, Kyunghoi KOO, Sujeong KIM, Juyoung KIM, Sanghune PARK, Jiyeon PARK, Jihun OH, Kyoungwon LEE
  • Clean data strobe signal generating circuit in read interface device
    Patent number: 10147481
    Abstract: A clean data strobe signal generating circuit in a read interface device includes receivers configured to output first and second single ended data strobe signals. In the circuit, a gate signal generating unit is configured to generate a data strobe gate signal synchronized with the first single ended data strobe signal using the first and second single ended data strobe signals and a memory gate signal of which the pulse width varies in accordance with a burst length after termination of a read latency. The gating unit is configured to generate a clean data strobe signal using the first single ended data strobe signal and the data strobe gate signal.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: December 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Daero Kim
  • CLEAN DATA STROBE SIGNAL GENERATING CIRCUIT IN READ INTERFACE DEVICE
    Publication number: 20170110175
    Abstract: Disclosed is a clean data strobe signal generating circuit in a read interface device. The clean data strobe signal generating circuit includes receivers configured to output first and second single ended data strobe signals. In the circuit, a gate signal generating unit is configured to generate a data strobe gate signal synchronized with the first single ended data strobe signal using the first and second single ended data strobe signals and a memory gate signal of which the pulse width varies in accordance with a burst length after termination of a read latency. The gating unit is configured to generate a clean data strobe signal using the first single ended data strobe signal and the data strobe gate signal.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 20, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Daero KIM