Abstract: A semiconductor memory device includes a mold structure including gate electrodes stacked on a first substrate, a channel structure that penetrates a first region of the mold structure to cross the gate electrodes, a first through structure that penetrates a second region of the mold structure, and a second through structure that penetrates a third region of the mold structure. The mold structure further includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell blocks and the dummy block includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.

Abstract: A mold structure includes gate electrodes stacked on a first substrate, a channel structure penetrating a first region of the mold structure to cross the gate electrodes, a first through structure penetrating a second region of the mold structure, and a second through structure penetrating a third region of the mold structure. The mold structure includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell and dummy blocks includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.

Abstract: The present disclosure relates to a coding test device and a coding test method. The coding test device according to one embodiment includes a problem provider for providing a test problem including an initial condition to a user terminal, a code receiver for receiving first algorithm code corresponding to the initial condition from the user terminal, and an additional condition provider for determining whether a predetermined passing condition for the first algorithm code is satisfied and providing an additional condition related to the initial condition to the user terminal based on the result of determination for the first algorithm code.

Abstract: A storage device having an improved operation speed includes memory blocks and a sudden power-off manager. The memory blocks connected to word lines as part of a super block. The sudden power-off manager in communication with the memory blocks and configured to, in response to a sudden power off, 1) select reference word lines among the word lines to group the word lines into word line zones defined using the reference word lines, 2) perform read operations on pages connected to the reference word lines to determine states of the pages connected to the reference word lines, 3) select a first erase page search zone among the word line zones based on results of the read operations, and 4) determine a first erase page located at a boundary between a program page and an erase page in the first erase page search zone.

Abstract: A storage device having an improved operation speed includes memory blocks and a sudden power-off manger. The memory blocks connected to word lines as part of a super block. The sudden power-off manager in communication with the memory blocks and configured to, in response to a sudden power off, 1) select reference word lines among the word lines to group the word lines into word line zones defined using the reference word lines, 2) perform read operations on pages connected to the reference word lines to determine states of the pages connected to the reference word lines, 3) select a first erase page search zone among the word line zones based on results of the read operations, and 4) determine a first erase page located at a boundary between a program page and an erase page in the first erase page search zone.

Abstract: A data storage device includes: a storage configured to generate a program completion signal when a data chunk is completely programmed; a buffer memory having a plurality of buffer regions configured to cache a plurality of data chunks, respectively; and a controller configured to receive a data chunk from a host device while a previously cached data chunk in the buffer memory is programmed to the storage; cache the received data chunk into the buffer memory; delete the programmed data chunk from the buffer memory in response to the program completion signal; receive a new data chunk from the host device; and cache the received new data chunk in an empty buffer region of the buffer memory.

Abstract: A memory system includes a storage medium including a memory region group having a plurality of memory regions; a memory configured to store a plurality of region read counts respectively corresponding to the plurality of memory regions and a group read count corresponding to the memory region group; a count management circuit configured to, when a first memory region among the plurality of memory regions is read-accessed, based on a first region read count corresponding to the first memory region among the plurality of region read counts, increase the group read count and reduce remaining region read counts other than the first region read count among the plurality of region read counts; and a reliability management circuit configured to perform a reliability management operation for the memory region group, based on the group read count.

Abstract: A memory system includes a storage medium including a memory region group having a plurality of memory regions; a memory configured to store a plurality of region read counts respectively corresponding to the plurality of memory regions and a group read count corresponding to the memory region group; a count management circuit configured to, when a first memory region among the plurality of memory regions is read-accessed, based on a first region read count corresponding to the first memory region among the plurality of region read counts, increase the group read count and reduce remaining region read counts other than the first region read count among the plurality of region read counts; and a reliability management circuit configured to perform a reliability management operation for the memory region group, based on the group read count.

Abstract: A method for operating a data storage device includes obtaining test data from a target region of a memory block by applying a test bias simultaneously to all word lines of the memory block; and estimating a state of the memory block based on the test data.

Abstract: A method for operating a data storage device includes obtaining test data from a target region of a memory block by applying a test bias simultaneously to all word lines of the memory block; and estimating a state of the memory block based on the test data.