Patents by Inventor Dae Sik Song
Dae Sik Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092141Abstract: An air conditioning device for a vehicle includes: a housing having an inside divided into an inflow space, a heat exchange space, and an outflow space, which are straightly arranged, and having a plurality of discharge ports, which communicates with an interior, at the inflow space; a blowing unit disposed at the inflow space of the housing and configured to blow air; a heat exchange unit disposed at the heat exchange space of the housing and configured to adjust a temperature of conditioned air by exchanging heat with air; and an opening-closing door disposed at the outflow space of the housing and configured to open and close the plurality of discharge ports such that conditioned air at an adjusted temperature selectively flows to the plurality of discharge ports. The air conditioning device adjusts the temperature of conditioned air for respective modes and reduces a flow resistance of air.Type: ApplicationFiled: March 8, 2023Publication date: March 21, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, DOOWON CLIMATE CONTROL CO., LTD.Inventors: Kwang Ok Han, Young Tae Song, Yong Chul Kim, Gee Young Shin, Su Yeon Kang, Jae Sik Choi, Dae Hee Lee, Byeong Moo Jang, Ung Hwi Kim, Jae Won Cha, Won Jun Joung, Byung Guk An
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Publication number: 20240079437Abstract: An image sensor includes a plurality of unit pixels, each including: a substrate including first and second sides which are opposite to each other, a photoelectric conversion layer in the substrate, and a wiring structure on the first side of the substrate. The wiring structure may include: a first capacitor, a second capacitor spaced from the first capacitor, a plurality of edge vias arranged along edges of the unit pixel, and a plurality of central vias interposed between the first capacitor and the second capacitor.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Inventors: KangMook LIM, Dae Hoon KIM, Seung Sik KIM, Ji-Youn SONG, Jae Hoon JEON, Dong Seok CHO
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Patent number: 7729177Abstract: A nonvolatile memory device implements a program routine followed by a program-verify routine when recording or modifying stored data. The nonvolatile memory device may include an array of memory cells for storing data, a sense node, and a gating circuit for selectively connecting a bitline of the array of memory cells to the sense node. The nonvolatile memory device may also include a page buffer coupled to the sense node. The page buffer may include a main latch for storing data to be written in the nonvolatile memory device, a cache latch for storing data supplied on an input line of the nonvolatile memory device to be transferred in the main latch through a source liner and a temporary static latch connected to the main latch through the source line and to the cache latch through an auxiliary switch and for transferring data between the main latch and the cache latch. The cache latch may be isolated from the source line during execution of the program routine and of the program-verify routine.Type: GrantFiled: June 7, 2007Date of Patent: June 1, 2010Inventors: Dae Sik Song, Jaeseok Park, Jacopo Mulatti
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Patent number: 7558152Abstract: An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.Type: GrantFiled: July 27, 2007Date of Patent: July 7, 2009Inventors: Hyungsang Lee, Dae Sik Song, Jacopo Mulatti
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Patent number: 7532512Abstract: A memory device includes a pre-charge transistor for connecting/disconnecting the input line of a global data line driver to a supply voltage line. To reduce the flow of current through the pre-charge transistor even in a stand-by state, the pre-charge transistor is turned on when, at a same time, an enabling signal of a page buffer is asserted, and a low voltage functioning mode is selected and the memory device is not in a stand-by state. Alternatively, the memory device may be in a stand-by state but the datum read from the memory is high. The pre-charge transistor is securely turned off in all other cases.Type: GrantFiled: August 3, 2007Date of Patent: May 12, 2009Assignees: STMicroelectronics Asia Pacific Pte. Ltd, Hynix Semicoductor, Inc.Inventors: Jaeseok Park, Dae Sik Song
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Publication number: 20090034351Abstract: A memory device includes a pre-charge transistor for connecting/disconnecting the input line of a global data line driver to a supply voltage line. To reduce the flow of current through the pre-charge transistor even in a stand-by state, the pre-charge transistor is turned on when, at a same time, an enabling signal of a page buffer is asserted, and a low voltage functioning mode is selected and the memory device is not in a stand-by state. Alternatively, the memory device may be in a stand-by state but the datum read from the memory is high. The pre-charge transistor is securely turned off in all other cases.Type: ApplicationFiled: August 3, 2007Publication date: February 5, 2009Applicants: STMicroelectronics Asia Pacific Pte Ltd, Hynix Semiconductor Inc.Inventors: Jaeseok Park, Dae Sik Song
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Publication number: 20080049542Abstract: An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.Type: ApplicationFiled: July 27, 2007Publication date: February 28, 2008Applicants: STMicroelectronics S.r.l., STMicroelectronics Asia Pacific Pte Ltd, Hynix Semiconductor Inc.Inventors: Hyungsang Lee, Dae Sik Song, Jacopo Mulatti
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Publication number: 20080028182Abstract: An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.Type: ApplicationFiled: July 27, 2007Publication date: January 31, 2008Applicants: STMicroelectronics S.r.I., STMicroelectronics Asia Pacific Pte Ltd, Hynix Semiconductor Inc.Inventors: Hyungsang LEE, Dae Sik SONG, Jacopo Mulatti
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Patent number: 6912677Abstract: A circuit for inspecting a data error is described herein. The circuit for inspecting a data error comprises a clock buffer, a buffer unit, a latch unit, a decoder, a compression unit, a counter, a data bus signal latch unit, and a select unit.Type: GrantFiled: November 14, 2002Date of Patent: June 28, 2005Assignee: Hynix Semiconductor Inc.Inventor: Dae Sik Song
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Publication number: 20030106000Abstract: A circuit for inspecting a data error is described herein. The circuit for inspecting a data error comprises a clock buffer, a buffer unit, a latch unit, a decoder, a compression unit, a counter, a data bus signal latch unit, and a select unit.Type: ApplicationFiled: November 14, 2002Publication date: June 5, 2003Inventor: Dae Sik Song
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Patent number: 6563760Abstract: Described inventions include circuits and methods for generating internal command signals in a semiconductor memory device. A testing time can be remarkably reduced by setting an internal clock signal having a predetermined cycle time shorter than that of an external clock signal of a test equipment, and generating internal command signals of the semiconductor memory device which synchronously respond to the internal clock signal. A command signal decoder composes the plurality of internal control signals. It then generates a test mode enable signal and a reversed test mode enable signal in response to a flag signal of internal address signals for precharging all the banks, and composes the reversed test mode enable signal and the plurality of internal control signals and then generates the internal command signals of the semiconductor memory device.Type: GrantFiled: December 31, 2001Date of Patent: May 13, 2003Assignee: Hynix Semiconductor Inc.Inventor: Dae Sik Song
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Publication number: 20020163850Abstract: Described inventions include circuits and methods for generating internal command signals in a semiconductor memory device. A testing time can be remarkably reduced by setting an internal clock signal having a predetermined cycle time shorter than that of an external clock signal of a test equipment, and generating internal command signals of the semiconductor memory device which synchronously respond to the internal clock signal. A command signal decoder composes the plurality of internal control signals. It then generates a test mode enable signal and a reversed test mode enable signal in response to a flag signal of internal address signals for precharging all the banks, and composes the reversed test mode enable signal and the plurality of internal control signals and then generates the internal command signals of the semiconductor memory device.Type: ApplicationFiled: December 31, 2001Publication date: November 7, 2002Inventor: Dae Sik Song
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Patent number: 6442097Abstract: In the virtual channel DRAM of the present invention, data can be transferred between one of the channels and a number of the segments in such a way to reduce test time for a whole chip.Type: GrantFiled: December 4, 2000Date of Patent: August 27, 2002Assignee: Hyundai Electronics Industries Co., LtdInventor: Dae-Sik Song
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Publication number: 20010005373Abstract: In the virtual channel DRAM of the present invention, data can be transferred between one of the channels and a number of the segments in such a way to reduce test time for a whole chip.Type: ApplicationFiled: December 4, 2000Publication date: June 28, 2001Inventor: Dae-Sik Song