Patents by Inventor Dae-Sin Kim
Dae-Sin Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038763Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.Type: ApplicationFiled: October 13, 2023Publication date: February 1, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Keun Hwi CHO, Sangdeok KWON, Dae Sin KIM, Dongwon KIM, Yonghee PARK, Hagju CHO
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Patent number: 11824059Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.Type: GrantFiled: July 7, 2021Date of Patent: November 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Keun Hwi Cho, Sangdeok Kwon, Dae Sin Kim, Dongwon Kim, Yonghee Park, Hagju Cho
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Publication number: 20230298154Abstract: A method for analyzing a wafer map using a wafer map analyzer includes generating first wafer maps each displaying characteristics of a first wafer for a corresponding channel of a plurality of channels. The first wafer maps are auto-encoded together to extract a first feature. The method also includes determining whether the first feature is a valid pattern, classifying the type of the first feature based on unsupervised learning when the first feature is a valid pattern and extracting a representative image of features classified into the same type as the first feature.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Inventors: MIN CHUL PARK, JEONG HOON KO, JI YONG PARK, JE HYUN LEE, DAE SIN KIM
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Publication number: 20230231026Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.Type: ApplicationFiled: August 18, 2022Publication date: July 20, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Seungkyu KIM, Yonghee PARK, Dong-Gwan SHIN, Dae Sin KIM, Sangyong KIM, Joohyung YOU
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Patent number: 11688050Abstract: A method for analyzing a wafer map using a wafer map analyzer includes generating first wafer maps each displaying characteristics of a first wafer for a corresponding channel of a plurality of channels. The first wafer maps are auto-encoded together to extract a first feature. The method also includes determining whether the first feature is a valid pattern, classifying the type of the first feature based on unsupervised learning when the first feature is a valid pattern and extracting a representative image of features classified into the same type as the first feature.Type: GrantFiled: April 24, 2018Date of Patent: June 27, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Min Chul Park, Jeong Hoon Ko, Ji Yong Park, Je Hyun Lee, Dae Sin Kim
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Publication number: 20220157853Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.Type: ApplicationFiled: July 7, 2021Publication date: May 19, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Keun Hwi CHO, Sangdeok KWON, Dae Sin KIM, Dongwon KIM, Yonghee PARK, Hagju CHO
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Patent number: 10217205Abstract: Provided are a method and system for analyzing grains using a high-resolution transmission electron microscopy (HRTEM) image. The method relates to analyzing nanometer grains, and includes receiving an HRTEM image, setting local windows each having a predetermined size for the HRTEM image, performing at least one Fast Fourier transformation on pixel data determined by the local windows to calculate local transformation data; and analyzing grains based on the local transformation data.Type: GrantFiled: March 10, 2016Date of Patent: February 26, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Min Chul Park, Dae Sin Kim, Sat Byul Kim, Sae Jin Kim, Zhiliang Xia, Je Hyun Lee
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Publication number: 20190050979Abstract: A method for analyzing a wafer map using a wafer map analyzer includes generating first wafer maps each displaying characteristics of a first wafer for a corresponding channel of a plurality of channels. The first wafer maps are auto-encoded together to extract a first feature. The method also includes determining whether the first feature is a valid pattern, classifying the type of the first feature based on unsupervised learning when the first feature is a valid pattern and extracting a representative image of features classified into the same type as the first feature.Type: ApplicationFiled: April 24, 2018Publication date: February 14, 2019Inventors: MIN CHUL PARK, JEONG HOON KO, JI YONG PARK, JE HYUN LEE, DAE SIN KIM
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Patent number: 9859288Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.Type: GrantFiled: April 30, 2015Date of Patent: January 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Woo Oh, Dae-Sin Kim, Young-Kwan Park, Keun-Ho Lee, Seon-Young Lee
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Patent number: 9831265Abstract: Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.Type: GrantFiled: May 26, 2016Date of Patent: November 28, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nambin Kim, Daewoong Kang, Dae Sin Kim, Kwang Soo Seol, Homin Son, Changsub Lee, Seunghyun Lim, Sunghoi Hur
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Patent number: 9786675Abstract: A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.Type: GrantFiled: February 15, 2016Date of Patent: October 10, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jaehun Jung, Zhiliang Xia, Daewoong Kang, Dae Sin Kim, Kwang Soo Seol, Homin Son, Seunghyun Lim
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Patent number: 9741735Abstract: A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.Type: GrantFiled: January 12, 2016Date of Patent: August 22, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Wook Lee, Daewoong Kang, Dae Sin Kim, Kwang Soo Seol, Homin Son, Seunghyun Lim
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Patent number: 9685519Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.Type: GrantFiled: June 2, 2015Date of Patent: June 20, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Na-Ra Kim, Seung-Hwan Kim, Sung-Hee Lee, Dae-Sin Kim, Ji-Young Kim, Dong-Soo Woo
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Publication number: 20160351582Abstract: Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.Type: ApplicationFiled: May 26, 2016Publication date: December 1, 2016Inventors: Nambin Kim, DAEWOONG KANG, DAE SIN KIM, KWANG SOO SEOL, HOMIN SON, CHANGSUB LEE, SEUNGHYUN LIM, SUNGHOI HUR
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Publication number: 20160267643Abstract: Provided are a method and system for analyzing grains using a high-resolution transmission electron microscopy (HRTEM) image. The method relates to analyzing nanometer grains, and includes receiving an HRTEM image, setting local windows each having a predetermined size for the HRTEM image, performing at least one Fast Fourier transformation on pixel data determined by the local windows to calculate local transformation data; and analyzing grains based on the local transformation data.Type: ApplicationFiled: March 10, 2016Publication date: September 15, 2016Inventors: MIN CHUL PARK, DAE SIN KIM, SAT BYUL KIM, SAE JIN KIM, ZHILIANG XIA, JE HYUN LEE
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Publication number: 20160240550Abstract: A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.Type: ApplicationFiled: February 15, 2016Publication date: August 18, 2016Inventors: JAEHUN JUNG, ZHILIANG XIA, DAEWOONG KANG, DAE SIN KIM, KWANG SOO SEOL, HOMIN SON, SEUNGHYUN LIM
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Publication number: 20160225786Abstract: A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.Type: ApplicationFiled: January 12, 2016Publication date: August 4, 2016Inventors: HYUN-WOOK LEE, DAEWOONG KANG, DAE SIN KIM, KWANG SOO SEOL, HOMIN SON, SEUNGHYUN LIM
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Patent number: 9293180Abstract: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage.Type: GrantFiled: May 29, 2014Date of Patent: March 22, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui-chul Jeong, Sung-hee Lee, Dae-sin Kim, Seung-hwan Kim, Dae-sun Kim, Sua Kim, Dong-soo Woo, Na-ra Kim
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Publication number: 20150263113Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.Type: ApplicationFiled: June 2, 2015Publication date: September 17, 2015Inventors: NA-RA KIM, SEUNG-HWAN KIM, SUNG-HEE LEE, DAE-SIN KIM, JI-YOUNG KIM, DONG-SOO WOO
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Publication number: 20150236028Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.Type: ApplicationFiled: April 30, 2015Publication date: August 20, 2015Inventors: Sang-Woo OH, Dae-Sin Kim, Young-Kwan Park, Keun-Ho Lee, Seon-Young Lee