Patents by Inventor DAE-SUB JUNG

DAE-SUB JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11545396
    Abstract: A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: January 3, 2023
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Deyan Chen, Mao Li, Dae-Sub Jung
  • Publication number: 20210376145
    Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 2, 2021
    Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Deyan Chen, Mao Li, Leong Tee Koh, Dae-Sub Jung
  • Patent number: 11121252
    Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 14, 2021
    Assignees: Semiconductor Manufacturing (Beijing) Intel Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventors: Deyan Chen, Mao Li, Leong Tee Koh, Dae-Sub Jung
  • Publication number: 20210028065
    Abstract: A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.
    Type: Application
    Filed: July 24, 2020
    Publication date: January 28, 2021
    Inventors: Deyan CHEN, Mao LI, Dae-Sub JUNG
  • Publication number: 20200273989
    Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.
    Type: Application
    Filed: October 15, 2019
    Publication date: August 27, 2020
    Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Deyan Chen, Mao Li, Leong Tee Koh, Dae-Sub Jung
  • Patent number: 10593781
    Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: March 17, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: De Yan Chen, Yan Chun Ma, Dae-Sub Jung
  • Patent number: 10411115
    Abstract: The present disclosure provides a method for forming a semiconductor device, including: forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate; forming an insulation structure between the mask layer and the substrate, and in the opening; performing a thinning process on the insulation structure exposed by the opening to form a recess region on a top of the insulation structure; and forming a gate electrode over the insulation structure and covering a portion of the recess region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: September 10, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Dae-Sub Jung, Lei Fang, Guang Li Yang, De Yan Chen
  • Patent number: 10340304
    Abstract: The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 2, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Dae-Sub Jung, Deyan Chen, Xuejie Shi
  • Publication number: 20180308893
    Abstract: The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.
    Type: Application
    Filed: June 26, 2018
    Publication date: October 25, 2018
    Inventors: Dae-Sub JUNG, Deyan CHEN, Xuejie SHI
  • Patent number: 10038027
    Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region; forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: July 31, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Dae-Sub Jung, Deyan Chen, Xuejie Shi
  • Publication number: 20170358661
    Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.
    Type: Application
    Filed: April 19, 2017
    Publication date: December 14, 2017
    Inventors: De Yan CHEN, Yan Chun MA, Dae-Sub JUNG
  • Publication number: 20170271482
    Abstract: The present disclosure provides a method for forming a semiconductor device, including: forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate; forming an insulation structure between the mask layer and the substrate, and in the opening; performing a thinning process on the insulation structure exposed by the opening to form a recess region on a top of the insulation structure; and forming a gate electrode over the insulation structure and covering a portion of the recess region.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Dae-Sub JUNG, Lei FANG, Guang Li YANG, De Yan CHEN
  • Publication number: 20170200758
    Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region: forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.
    Type: Application
    Filed: January 3, 2017
    Publication date: July 13, 2017
    Applicant: Semiconductor Manufacturing International (Beijing)
    Inventors: Dae-Sub JUNG, Deyan CHEN, Xuejie SHI
  • Patent number: 9536742
    Abstract: The present disclosure provides a method for forming a Lateral Double-Diffused MOSFET (LDMOS). The method includes providing a semiconductor substrate having a first conductivity type; forming a first shallow trench isolation (STI) structure in the semiconductor substrate; and applying a first ion implantation to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure. The method also includes applying a counter-doping implantation to form a counter-doped region having the first conductivity in the drift region and forming a body region on one side of the drift region in the semiconductor substrate. The method further includes forming a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 3, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Dae-Sub Jung, Guohao Cao
  • Publication number: 20150364598
    Abstract: The present disclosure provides a method for forming a Lateral Double-Diffused MOSFET (LDMOS). The method includes providing a semiconductor substrate having a first conductivity type; forming a first shallow trench isolation (STI) structure in the semiconductor substrate; and applying a first ion implantation to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure. The method also includes applying a counter-doping implantation to form a counter-doped region having the first conductivity in the drift region and forming a body region on one side of the drift region in the semiconductor substrate. The method further includes forming a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 17, 2015
    Inventors: DAE-SUB JUNG, GUOHAO CAO