Patents by Inventor DAE-SUB JUNG
DAE-SUB JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11545396Abstract: A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.Type: GrantFiled: July 24, 2020Date of Patent: January 3, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Deyan Chen, Mao Li, Dae-Sub Jung
-
Patent number: 11239358Abstract: A semiconductor structure and fabrication method are provided. The method includes: providing a substrate with a first doped region and a second doped region; forming discrete first isolation structures in the second doped region; forming a third doped region in the second doped region between adjacent first isolation structures and under the first isolation structures; forming a gate structure; forming a source region in the first doped region; and forming a drain region in the second doped region. The first doped region includes first doping ions and the second doped region includes second doping ions with a conductivity type opposite to a conductivity type of the first doping ions. The third doped region includes third doping ions with a conductivity type opposite to the conductivity type of the second doping ions. A portion of the first isolation structure is located between the gate structure and the drain region.Type: GrantFiled: January 17, 2020Date of Patent: February 1, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Mao Li, Dae Sub Jung, De Yan Chen
-
Publication number: 20210376145Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventors: Deyan Chen, Mao Li, Leong Tee Koh, Dae-Sub Jung
-
Patent number: 11121252Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.Type: GrantFiled: October 15, 2019Date of Patent: September 14, 2021Assignees: Semiconductor Manufacturing (Beijing) Intel Corporation, Semiconductor Manufacturing (Shanghai) International CorporationInventors: Deyan Chen, Mao Li, Leong Tee Koh, Dae-Sub Jung
-
Publication number: 20210028065Abstract: A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.Type: ApplicationFiled: July 24, 2020Publication date: January 28, 2021Inventors: Deyan CHEN, Mao LI, Dae-Sub JUNG
-
Patent number: 10804105Abstract: A semiconductor device and its manufacturing method, relating to semiconductor techniques. The semiconductor device manufacturing method comprises: forming a patterned first hard mask layer on a substrate to define a position for buried layers; conducting a first ion implantation using the first hard mask layer as a mask to form a first buried layer and a second buried layer both having a first conductive type and separated from each other at two sides of the first hard mask layer in the substrate; conducting a second ion implantation to form a separation region with a second conductive type opposite to the first conductive type in the substrate between the first and the second buried layers; removing the first hard mask layer; and forming a semiconductor layer on the substrate. This inventive concept reduces an area budget of a substrate and simplifies the manufacturing process.Type: GrantFiled: February 19, 2020Date of Patent: October 13, 2020Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Dae Sub Jung, De Yan Chen, Guang Li Yang
-
Publication number: 20200273989Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.Type: ApplicationFiled: October 15, 2019Publication date: August 27, 2020Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventors: Deyan Chen, Mao Li, Leong Tee Koh, Dae-Sub Jung
-
Publication number: 20200251590Abstract: A semiconductor structure and fabrication method are provided. The method includes: providing a substrate with a first doped region and a second doped region; forming discrete first isolation structures in the second doped region; forming a third doped region in the second doped region between adjacent first isolation structures and under the first isolation structures; forming a gate structure; forming a source region in the first doped region; and forming a drain region in the second doped region. The first doped region includes first doping ions and the second doped region includes second doping ions with a conductivity type opposite to a conductivity type of the first doping ions. The third doped region includes third doping ions with a conductivity type opposite to the conductivity type of the second doping ions. A portion of the first isolation structure is located between the gate structure and the drain region.Type: ApplicationFiled: January 17, 2020Publication date: August 6, 2020Inventors: Mao LI, Dae Sub JUNG, De Yan CHEN
-
Publication number: 20200185223Abstract: A semiconductor device and its manufacturing method, relating to semiconductor techniques. The semiconductor device manufacturing method comprises: forming a patterned first hard mask layer on a substrate to define a position for buried layers; conducting a first ion implantation using the first hard mask layer as a mask to form a first buried layer and a second buried layer both having a first conductive type and separated from each other at two sides of the first hard mask layer in the substrate; conducting a second ion implantation to form a separation region with a second conductive type opposite to the first conductive type in the substrate between the first and the second buried layers; removing the first hard mask layer; and forming a semiconductor layer on the substrate. This inventive concept reduces an area budget of a substrate and simplifies the manufacturing process.Type: ApplicationFiled: February 19, 2020Publication date: June 11, 2020Inventors: Dae Sub JUNG, De Yan CHEN, Guang Li YANG
-
Patent number: 10600650Abstract: A semiconductor device and its manufacturing method, relating to semiconductor techniques. The semiconductor device manufacturing method comprises: forming a patterned first hard mask layer on a substrate to define a position for buried layers; conducting a first ion implantation using the first hard mask layer as a mask to form a first buried layer and a second buried layer both having a first conductive type and separated from each other at two sides of the first hard mask layer in the substrate; conducting a second ion implantation to form a separation region with a second conductive type opposite to the first conductive type in the substrate between the first and the second buried layers; removing the first hard mask layer; and forming a semiconductor layer on the substrate. This inventive concept reduces an area budget of a substrate and simplifies the manufacturing process.Type: GrantFiled: April 27, 2018Date of Patent: March 24, 2020Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Dae Sub Jung, De Yan Chen, Guang Li Yang
-
Patent number: 10593781Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.Type: GrantFiled: April 19, 2017Date of Patent: March 17, 2020Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: De Yan Chen, Yan Chun Ma, Dae-Sub Jung
-
Patent number: 10490629Abstract: A method for forming power semiconductor device is provided. The power semiconductor device includes a substrate having a device region and a surrounding termination region; and at least a power device formed in the device region of the substrate. The power semiconductor substrate also includes a termination structure having a plurality of semiconductor plugs formed in a first surface of the termination region of the substrate. Wherein the plurality of the semiconductor plugs are formed in a plurality of ring trenches formed in the first surface of the substrate in the termination regions, with a semiconductor plug formed in each of the plurality of ring trenches.Type: GrantFiled: June 26, 2018Date of Patent: November 26, 2019Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Dae Sub Jung, Bo Liu, Roger To-Hoi Szeto
-
Patent number: 10411115Abstract: The present disclosure provides a method for forming a semiconductor device, including: forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate; forming an insulation structure between the mask layer and the substrate, and in the opening; performing a thinning process on the insulation structure exposed by the opening to form a recess region on a top of the insulation structure; and forming a gate electrode over the insulation structure and covering a portion of the recess region.Type: GrantFiled: June 5, 2017Date of Patent: September 10, 2019Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Dae-Sub Jung, Lei Fang, Guang Li Yang, De Yan Chen
-
Patent number: 10340304Abstract: The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.Type: GrantFiled: June 26, 2018Date of Patent: July 2, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Dae-Sub Jung, Deyan Chen, Xuejie Shi
-
Publication number: 20180315603Abstract: A semiconductor device and its manufacturing method, relating to semiconductor techniques. The semiconductor device manufacturing method comprises: forming a patterned first hard mask layer on a substrate to define a position for buried layers; conducting a first ion implantation using the first hard mask layer as a mask to form a first buried layer and a second buried layer both having a first conductive type and separated from each other at two sides of the first hard mask layer in the substrate; conducting a second ion implantation to form a separation region with a second conductive type opposite to the first conductive type in the substrate between the first and the second buried layers; removing the first hard mask layer; and forming a semiconductor layer on the substrate. This inventive concept reduces an area budget of a substrate and simplifies the manufacturing process.Type: ApplicationFiled: April 27, 2018Publication date: November 1, 2018Inventors: Dae Sub JUNG, De Yan CHEN, Guang Li YANG
-
Publication number: 20180308893Abstract: The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.Type: ApplicationFiled: June 26, 2018Publication date: October 25, 2018Inventors: Dae-Sub JUNG, Deyan CHEN, Xuejie SHI
-
Publication number: 20180308932Abstract: A method for forming power semiconductor device is provided. The power semiconductor device includes a substrate having a device region and a surrounding termination region; and at least a power device formed in the device region of the substrate. The power semiconductor substrate also includes a termination structure having a plurality of semiconductor plugs formed in a first surface of the termination region of the substrate. Wherein the plurality of the semiconductor plugs are formed in a plurality of ring trenches formed in the first surface of the substrate in the termination regions, with a semiconductor plug formed in each of the plurality of ring trenches.Type: ApplicationFiled: June 26, 2018Publication date: October 25, 2018Inventors: DAE SUB JUNG, BO LIU, ROGER TO-HOI SZETO
-
Patent number: 10090403Abstract: A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and forming a plurality of trenches in the second surface of the substrate. The method also includes forming a semiconductor pillar in each of the plurality of trenches, wherein the semiconductor pillars and the substrate form a plurality of super junctions of the power semiconductor device for increasing the breakdown voltage of the power semiconductor device and reducing the on-stage voltage of the power semiconductor device; and forming a gate structure on the first surface of the substrate. Further, the method includes forming a plurality of well regions in the first surface of the substrate around the gate structure; and forming a source region in each of the plurality of well regions around the gate structure.Type: GrantFiled: June 15, 2017Date of Patent: October 2, 2018Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Dae Sub Jung, Bo Liu
-
Patent number: 10038027Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region; forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.Type: GrantFiled: January 3, 2017Date of Patent: July 31, 2018Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Dae-Sub Jung, Deyan Chen, Xuejie Shi
-
Patent number: 10032865Abstract: A power semiconductor device is provided. The power semiconductor device includes a substrate having a device region and a surrounding termination region; and at least a power device formed in the device region of the substrate. The power semiconductor substrate also includes a termination structure having a plurality of semiconductor plugs formed in a first surface of the termination region of the substrate. Wherein the plurality of the semiconductor plugs are formed in a plurality of ring trenches formed in the first surface of the substrate in the termination regions, with a semiconductor plug formed in each of the plurality of ring trenches.Type: GrantFiled: February 8, 2016Date of Patent: July 24, 2018Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Dae Sub Jung, Bo Liu, Roger To-Hoi Szeto