Patents by Inventor DAE-SUB JUNG
DAE-SUB JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11545396Abstract: A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.Type: GrantFiled: July 24, 2020Date of Patent: January 3, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Deyan Chen, Mao Li, Dae-Sub Jung
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Publication number: 20210376145Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventors: Deyan Chen, Mao Li, Leong Tee Koh, Dae-Sub Jung
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Patent number: 11121252Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.Type: GrantFiled: October 15, 2019Date of Patent: September 14, 2021Assignees: Semiconductor Manufacturing (Beijing) Intel Corporation, Semiconductor Manufacturing (Shanghai) International CorporationInventors: Deyan Chen, Mao Li, Leong Tee Koh, Dae-Sub Jung
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Publication number: 20210028065Abstract: A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.Type: ApplicationFiled: July 24, 2020Publication date: January 28, 2021Inventors: Deyan CHEN, Mao LI, Dae-Sub JUNG
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Publication number: 20200273989Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.Type: ApplicationFiled: October 15, 2019Publication date: August 27, 2020Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventors: Deyan Chen, Mao Li, Leong Tee Koh, Dae-Sub Jung
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Patent number: 10593781Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.Type: GrantFiled: April 19, 2017Date of Patent: March 17, 2020Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: De Yan Chen, Yan Chun Ma, Dae-Sub Jung
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Patent number: 10411115Abstract: The present disclosure provides a method for forming a semiconductor device, including: forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate; forming an insulation structure between the mask layer and the substrate, and in the opening; performing a thinning process on the insulation structure exposed by the opening to form a recess region on a top of the insulation structure; and forming a gate electrode over the insulation structure and covering a portion of the recess region.Type: GrantFiled: June 5, 2017Date of Patent: September 10, 2019Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Dae-Sub Jung, Lei Fang, Guang Li Yang, De Yan Chen
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Patent number: 10340304Abstract: The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.Type: GrantFiled: June 26, 2018Date of Patent: July 2, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Dae-Sub Jung, Deyan Chen, Xuejie Shi
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Publication number: 20180308893Abstract: The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.Type: ApplicationFiled: June 26, 2018Publication date: October 25, 2018Inventors: Dae-Sub JUNG, Deyan CHEN, Xuejie SHI
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Patent number: 10038027Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region; forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.Type: GrantFiled: January 3, 2017Date of Patent: July 31, 2018Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Dae-Sub Jung, Deyan Chen, Xuejie Shi
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Publication number: 20170358661Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.Type: ApplicationFiled: April 19, 2017Publication date: December 14, 2017Inventors: De Yan CHEN, Yan Chun MA, Dae-Sub JUNG
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Publication number: 20170271482Abstract: The present disclosure provides a method for forming a semiconductor device, including: forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate; forming an insulation structure between the mask layer and the substrate, and in the opening; performing a thinning process on the insulation structure exposed by the opening to form a recess region on a top of the insulation structure; and forming a gate electrode over the insulation structure and covering a portion of the recess region.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Dae-Sub JUNG, Lei FANG, Guang Li YANG, De Yan CHEN
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Publication number: 20170200758Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region: forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.Type: ApplicationFiled: January 3, 2017Publication date: July 13, 2017Applicant: Semiconductor Manufacturing International (Beijing)Inventors: Dae-Sub JUNG, Deyan CHEN, Xuejie SHI
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Patent number: 9536742Abstract: The present disclosure provides a method for forming a Lateral Double-Diffused MOSFET (LDMOS). The method includes providing a semiconductor substrate having a first conductivity type; forming a first shallow trench isolation (STI) structure in the semiconductor substrate; and applying a first ion implantation to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure. The method also includes applying a counter-doping implantation to form a counter-doped region having the first conductivity in the drift region and forming a body region on one side of the drift region in the semiconductor substrate. The method further includes forming a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region.Type: GrantFiled: June 12, 2015Date of Patent: January 3, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Dae-Sub Jung, Guohao Cao
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Publication number: 20150364598Abstract: The present disclosure provides a method for forming a Lateral Double-Diffused MOSFET (LDMOS). The method includes providing a semiconductor substrate having a first conductivity type; forming a first shallow trench isolation (STI) structure in the semiconductor substrate; and applying a first ion implantation to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure. The method also includes applying a counter-doping implantation to form a counter-doped region having the first conductivity in the drift region and forming a body region on one side of the drift region in the semiconductor substrate. The method further includes forming a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region.Type: ApplicationFiled: June 12, 2015Publication date: December 17, 2015Inventors: DAE-SUB JUNG, GUOHAO CAO