Abstract: Disclosed herein are an apparatus and method for processing vehicle data security based on a cloud.

Abstract: A structure and method for utilizing natural light indoors or in the interior in a moving space are disclosed. The method includes: determining, by a controller, whether or not current indoor information is confirmable; determining, by the controller, whether or not the current indoor information coincides with a user request signal, upon determining that the current indoor information is confirmable; controlling, by the controller, radiation amounts of the natural light and artificial light, upon determining that the current indoor information does not coincide with the user request signal; and adjusting, by the controller, a position value of a smart lamp unit.

Abstract: A structure and method for utilizing natural light indoors or in the interior in a moving space are disclosed. The structure includes: at least one natural light condenser configured to reflect the natural light; a natural light transmitter configured such that the natural light reflected by the at least one natural light condenser is moved to the natural light transmitter; a smart lamp unit including an artificial light generator; a smart lamp driver located adjacent to the smart lamp unit and configured to move the smart lamp unit; and a controller connected to the at least one natural light condenser, the natural light transmitter, the smart lamp unit, and the smart lamp driver so as to transmit and receive information therewith. The controller is configured to combine artificial light with the natural light in response to a user request signal to radiate a combination of the artificial and natural light.

Abstract: Embodiments of the present disclosure includes an apparatus for estimating the state of charge of a battery, comprising: a first coulomb counter (STCC) for sampling a first charge variation (?Q) on the battery in a time comprising a number of predetermined periods, by adding up a battery current Im in each of the predetermined periods; a compensator for calculating a second charge variation (?Q_comp) by compensating for the first charge variation (?Q); a second coulomb counter (CCE) for calculating a first predicted charge amount (Qe) by adding up the second charge variation (?Q_comp); and a state of charge estimator for estimating the state of charge of the battery on the basis of the first predicted charge amount (Qe). The technique increases the accuracy of a state of charge estimation by compensating for characteristics according to battery temperature and aging.

Abstract: A structure and method for utilizing natural light indoors or in the interior in a moving space are disclosed. The structure includes: at least one natural light condenser configured to reflect the natural light; a natural light transmitter configured such that the natural light reflected by the at least one natural light condenser is moved to the natural light transmitter; a smart lamp unit including an artificial light generator; a smart lamp driver located adjacent to the smart lamp unit and configured to move the smart lamp unit; and a controller connected to the at least one natural light condenser, the natural light transmitter, the smart lamp unit, and the smart lamp driver so as to transmit and receive information therewith. The controller is configured to combine artificial light with the natural light in response to a user request signal to radiate a combination of the artificial and natural light.

Abstract: A semiconductor memory apparatus includes a memory cell unit and an internal voltage stabilization apparatus. The memory cell unit includes a row decoder, a column decoder, and a memory cell array. The internal voltage stabilization apparatus includes an operation termination determination unit configured to determine whether an operation of the semiconductor memory apparatus is terminated on the basis of an external input voltage and output an operation termination command, a termination voltage generation unit configured to generate a termination voltage having a preset voltage value on the basis of a determination result of operation termination by the operation termination determination unit, and a switch unit. The switch unit includes a plurality of switches that are turned in response to the operation termination command, and supplies the termination voltage, input from the termination voltage generation unit, to a plurality of internal nodes of the memory cell array.

Abstract: A semiconductor memory apparatus includes a memory cell unit and an internal voltage stabilization apparatus. The memory cell unit includes a row decoder, a column decoder, and a memory cell array. The internal voltage stabilization apparatus includes an operation termination determination unit configured to determine whether an operation of the semiconductor memory apparatus is terminated on the basis of an external input voltage and output an operation termination command, a termination voltage generation unit configured to generate a termination voltage having a preset voltage value on the basis of a determination result of operation termination by the operation termination determination unit, and a switch unit. The switch unit includes a plurality of switches that are turned in response to the operation termination command, and supplies the termination voltage, input from the termination voltage generation unit, to a plurality of internal nodes of the memory cell array.

Abstract: A dynamic random access memory (DRAM) device includes a memory cell array including a first sub memory cell array block including a plurality of first memory cells between a plurality of first sub word lines, and a plurality of first odd-numbered bit lines and a plurality of dummy bit lines and includes a second sub memory cell array block including a plurality of second memory cells between a plurality of second sub word lines, a plurality of second odd-numbered bit lines, and a plurality of second even-numbered bit lines. The memory cell array may be arranged to have an open bit line architecture in which the plurality of first odd-numbered bit lines and the plurality of second even-numbered bit lines form bit line pairs.

Abstract: A dynamic random access memory (DRAM) device includes a memory cell array including a first sub memory cell array block including a plurality of first memory cells between a plurality of first sub word lines, and a plurality of first odd-numbered bit lines and a plurality of dummy bit lines and includes a second sub memory cell array block including a plurality of second memory cells between a plurality of second sub word lines, a plurality of second odd-numbered bit lines, and a plurality of second even-numbered bit lines. The memory cell array may be arranged to have an open bit line architecture in which the plurality of first odd-numbered bit lines and the plurality of second even-numbered bit lines form bit line pairs.

Abstract: A semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into the element isolation region and penetrating the active region, and a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.

Abstract: A semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into the element isolation region and penetrating the active region, and a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage.

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract: A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.

Abstract: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage.

Abstract: A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.

Abstract: There are provided a semiconductor memory device and a burn-in test method thereof. A semiconductor memory device according to an aspect of the invention includes a plurality of memory cell blocks, each of which includes a plurality of memory cells that are respectively coupled to a plurality of word lines and a plurality of bit lines, a word line control unit activating word lines in memory cell blocks that correspond to row address signals and word lines in memory cell blocks that do not correspond to the row address signals, during a test operation, and a write circuit writing data in the memory cell blocks that correspond to the row address signals and not writing data in the memory cell blocks that do not correspond to the row address signals, during the test operation.

Abstract: There are provided a semiconductor memory device and a burn-in test method thereof. A semiconductor memory device according to an aspect of the invention includes a plurality of memory cell blocks, each of which includes a plurality of memory cells that are respectively coupled to a plurality of word lines and a plurality of bit lines, a word line control unit activating word lines in memory cell blocks that correspond to row address signals and word lines in memory cell blocks that do not correspond to the row address signals, during a test operation, and a write circuit writing data in the memory cell blocks that correspond to the row address signals and not writing data in the memory cell blocks that do not correspond to the row address signals, during the test operation.

Abstract: Integrated circuit devices and methods of operating same include a delayed locked loop (DLL) circuit that can be operated at a high frequency during a normal operation mode and during a test mode. The test mode may be, for example, for performing burn-in testing. For example, an integrated circuit device may include a DLL control circuit that generates a control signal that is responsive to a test mode signal. An oscillator circuit may generate a clock signal that is responsive to the test mode signal. This clock signal may be a high frequency clock signal, such as that used to drive a DLL circuit during a normal operation mode. A DLL circuit, which is responsive to the clock signal, may be configured to operate in either a test mode or a normal operation mode based on the control signal. By generating the clock signal at a high frequency, the DLL circuit may be evaluated during burn-in testing, for example, under conditions that are comparable to conditions during normal operation.