Patents by Inventor Dae Sung Kim

Dae Sung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210320673
    Abstract: An error correction circuit includes: a first error correction encoder for generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages; a second error correction encoder for generating a plurality of column-codewords; a first error correction decoder for performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and outputting a soft information of the first error correction decoding; and a second error correction decoder for determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.
    Type: Application
    Filed: September 18, 2020
    Publication date: October 14, 2021
    Inventors: Dae Sung KIM, Hyun Jun LEE
  • Patent number: 11143844
    Abstract: An embodiment provides an imaging lens comprising first to third lens groups arranged sequentially from an object side to an image side and having refractive power, wherein the distances of the second lens group and the third lens group from the first lens group are variable such that a tele mode having a narrow angle of view and a wide mode having a wide angle of view can be implemented, the EFL in the tele mode is no more than 2.5 times the EFL in the wide mode, 2<Fnumber<5 and 15 mm<TTL?40 mm.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: October 12, 2021
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Ji Sung Kim, Dae Sik Jang, Soo Min Jeong
  • Publication number: 20210306003
    Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of non-volatile memory groups individually storing a plurality of data segments, each data segment corresponding to a codeword. The controller is configured to perform hard decision decoding to correct an error when the error is included in a first data segment among the plurality of data segments, determine whether other data segments associated with the first data segment, among the plurality of data segments, are readable when the hard decision decoding fails, and perform chipkill decoding based on the first data segment and the other data segments when the other data segments are readable.
    Type: Application
    Filed: October 5, 2020
    Publication date: September 30, 2021
    Inventors: Dae Sung KIM, Seung Gu JI
  • Patent number: 11130486
    Abstract: A limp-home control method for a hybrid vehicle may include: a fault determination step for determining, by a controller, whether a solenoid valve battery short circuit fault occurs in a transmission; a first limp-home step for controlling, by the controller, solenoid valves to implement a limp-home gear stage while maintaining a state where power is suppliable to the solenoid valves involved in shifting gears when it is determined that the solenoid valve battery short circuit fault exists; an engine necessity verification step for verifying, by the controller, whether engagement of an engine clutch is needed; and a second limp-home step for driving, by the controller, a solenoid valve controlling the engine clutch to engage the engine clutch, implementing limp-home driving by engine power when the engagement of the engine clutch is needed.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 28, 2021
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Sang Hyun Jeong, Hak Sung Lee, Seong Hwan Kim, Dae Won Yang, Gyeong Cheol Kim
  • Patent number: 11130245
    Abstract: A parallel type integrated actuator is proposed. The actuator includes: a driving unit composed of a first motor, a second motor, a third motor, and a fourth motor; a first shaft, a second shaft, and a third shaft, each shaft being inserted into each other through a hollow structure and forming a co-axis, each shaft being capable of rotating relative to each other in an inserted state, and each shaft having the other end part thereof extending outside the driving unit; an distal end part disposed outside the driving unit and on which an actuator is mounted; a first link part, a second link part, and a third link part allowing the distal end part to rotate in pitching, yawing, and rolling directions; and a universal link part connecting the fourth rotor, which is a rotor of the fourth motor, and the distal end part to each other.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: September 28, 2021
    Assignee: Ezwon Tnternet Service Co., Ltd.
    Inventors: Jae Ho Noh, Jae Yong Lee, Dae Je Kim, Jae Sung Kwon, Woo Sung Yang, Jin Ho Yang, Hyun Kuk Lim
  • Publication number: 20210294429
    Abstract: A method of controlling a user interface using an input image is provided. The method includes storing operation executing information of each of one or more gesture forms according to each of a plurality of functions, detecting a gesture form from the input image, and identifying the operation executing information mapped on the detected gesture form to execute an operation according to a function which is currently operated.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 23, 2021
    Inventors: Jin-Yong KIM, Ji-Young KANG, Dae-Sung KIM, Seok-Tae KIM, Bo-Young LEE, Seung-Kyung LIM, Jin-Young JEON
  • Patent number: 11128315
    Abstract: Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Myung Jin Jo, Dae Sung Kim, Wan Je Sung
  • Patent number: 11121007
    Abstract: An apparatus for supplying chemical liquid may include a chemical liquid discharging member, a reservoir, a chemical liquid supplying member and a chemical liquid circulating member. The chemical liquid discharging member may discharge a chemical liquid onto a substrate. The reservoir may store the chemical liquid supplied to the chemical liquid discharging member. The chemical liquid supplying member may supply the chemical liquid stored in the reservoir. The chemical liquid circulating member may circulate the chemical liquid from the chemical liquid discharging member to the reservoir.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: September 14, 2021
    Inventors: Jae-Youl Kim, Jeeyong Jung, Young Ho Seo, Dae Sung Kim, Beomjeong Oh, Kwangbok Jun, Hyungoo Kwon, Sanguk Son
  • Patent number: 11115064
    Abstract: Provided herein is an error correction decoder and a memory system having the same. The error correction decoder includes a memory configured to store a hard decision value of a variable node. The decoder further includes a flipping function value generator configured to generate, in an i-th iteration, a first value based on a number of unsatisfied check nodes (UCNs) corresponding to the variable node, and to generate a flipping function value as (i) a difference between the first value and an offset value or (ii) a set value, wherein i is a non-negative integer. The decoder also includes a comparator configured to output, in the i-th iteration, a first signal indicating whether to flip or not flip the hard decision value of the variable node in the memory based on comparing the flipping function value to a flipping threshold value.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Bo Seok Jeong, Soon Young Kang, Dae Sung Kim
  • Patent number: 11114009
    Abstract: Disclosed is a display device including a display panel having a plurality of pixels, each of the pixels including at least two subpixels, the display panel including a first display area and a second display area, the second display area being disposed to overlap an optical module, a memory configured to store shape information of the second display area including position information of a starting point, vertical length information of the second display area, and line-based direction information and width information indicating the border of the second display area, and a controller configured to change an image that is displayed in at least one of the first display area and the second display area using the shape information of the second display area and to perform control such that the changed image is displayed on the display panel.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: September 7, 2021
    Assignee: SILICON WORKS CO., LTD.
    Inventors: Dae Hee Bae, Bo Sung Kim, Jun Hun Park, Ji Hong Yuk, Sung Woo Han, Ji Hoon Choi
  • Publication number: 20210264986
    Abstract: A memory system includes a memory device including a plane including a plurality of memory blocks, each memory block including a plurality of memory cells, each memory cell capable of storing multi-bit data, and a controller configured to determine that a second memory block is a candidate block when an issue-triggering operation is performed for a first memory block, adjust levels of read voltages when receiving a read command for data stored in the second memory block determined as the candidate block, and control the memory device to supply adjusted levels of the read voltages to the second memory block to perform a read operation corresponding to the read command. The second memory block and the first memory block are included in the same plane. The issue-triggering operation includes either a program operation or an erase operation.
    Type: Application
    Filed: July 14, 2020
    Publication date: August 26, 2021
    Inventor: Dae Sung KIM
  • Patent number: 11095310
    Abstract: An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Won Gyu Shin
  • Patent number: 11088330
    Abstract: The purpose of the present invention is to provide a compound that can improve the lifespan, low drive voltage and high luminous efficiency of an element, an organic electronic element using same, and an electronic device comprising same.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 10, 2021
    Inventors: Yun Suk Lee, Seul-gi Kim, Dae Sung Kim, Ki Ho So, Dae Hwan Oh, Jin Ho Yun, Bum Sung Lee, Seong Je Park
  • Publication number: 20210241834
    Abstract: A memory system includes a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and a controller configured to detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group, search for a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation.
    Type: Application
    Filed: September 3, 2020
    Publication date: August 5, 2021
    Inventors: Sang Sik KIM, Dae Sung KIM
  • Publication number: 20210242410
    Abstract: Provided is an organic electric element and an electronic device thereof, by using the mixture of the compounds as a phosphorescent host material, it is possible to achieve a high luminous efficiency and a low driving voltage of an organic electric element, and the life span of the device can be greatly improved.
    Type: Application
    Filed: March 25, 2021
    Publication date: August 5, 2021
    Applicant: DUK SAN NEOLUX CO., LTD.
    Inventors: Mun Jae LEE, Soung Yun MUN, Jae Taek KWON, Dae Sung KIM, Moo Jin PARK, Sun Hee LEE, Sun Pil HWANG, Ho Young JUNG, Bum Sung LEE
  • Patent number: 11082068
    Abstract: An error correction circuit using a BCH code may include a decoder performing at least one of a first error correction decoding using a first error correction capability or a second error correction decoding using a second error correction capability and an encoder generating a codeword based on a message and a generation matrix corresponding to the first error correction capability and generating an additional parity based on the codeword and one or more rows of a parity check matrix corresponding to the second error correction capability, wherein a syndrome vector generated based on a read vector corresponding to the codeword is used during the first error correction decoding and an additional syndrome generated based on the additional parity is used during the second error correction decoding, and wherein the one or more rows are extended from a parity check matrix corresponding to the first error correction capability.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 3, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Kwang Hyun Kim
  • Patent number: 11061480
    Abstract: A method of controlling a user interface using an input image is provided. The method includes storing operation executing information of each of one or more gesture forms according to each of a plurality of functions, detecting a gesture form from the input image, and identifying the operation executing information mapped on the detected gesture form to execute an operation according to a function which is currently operated.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Yong Kim, Ji-Young Kang, Dae-Sung Kim, Seok-Tae Kim, Bo-Young Lee, Seung-Kyung Lim, Jin-Young Jeon
  • Publication number: 20210211141
    Abstract: The present technology includes an electronic device and a method of operating the same using an artificial neural network. The electronic device according to the present technology includes a decoding controller inputting a primary syndrome vector generated based on a read vector and a parity check matrix to a trained artificial neural network to a trained artificial neural network, and selecting any one of a first error correction decoding algorithm and a second error correction decoding algorithm based on an output of the trained artificial neural network corresponding to the input, and an error correction decoder performing error correction decoding on a read vector using the selected error correction decoding algorithm. The output of the trained artificial neural network includes a first predicted value indicating a probability that a first error correction decoding using the first error correction decoding algorithm is successful.
    Type: Application
    Filed: July 8, 2020
    Publication date: July 8, 2021
    Inventors: Dae Sung Kim, Soon Young Kang, Jang Seob Kim
  • Publication number: 20210208813
    Abstract: A memory system may include a memory device and a memory controller. The memory device may include memory cells. The memory controller may estimate and use an read voltage to distinguish one or more memory cells corresponding to a first threshold voltage distribution from one or more memory cells corresponding to a second threshold voltage distribution, the read voltage being estimated based on standard deviations and average threshold voltages of the first and the second threshold voltage distributions and probability density functions corresponding to the first and the second threshold voltage distributions, respectively. The memory controller may be structured and operable to calculate the standard deviation of the first threshold voltage distribution, based on a first probability area distinguished by a first target read voltage, a second probability area distinguished by a second target read voltage, and inverse Q-function values corresponding to the first and the second probability areas.
    Type: Application
    Filed: July 14, 2020
    Publication date: July 8, 2021
    Inventors: Dae Sung Kim, Kyung Bum Kim
  • Patent number: 11055164
    Abstract: There are provided an error correction decoder and a memory system having the same. The error correction decoder includes a node processor for performing at least one iteration of an error correction decoding based on at least one parameter used for an iterative decoding, a reliability information generator for generating reliability information corresponding to a current iteration upon a determination that the error correction decoding corresponding to the current iteration has been unsuccessful, and a parameter adjuster for adjusting the at least one parameter upon a determination that the reliability information satisfies a predetermined condition, and controlling the node processor to perform a next iteration based on the adjusted.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Soon Young Kang, Dae Sung Kim, Wan Je Sung, Myung Jin Jo, Jae Young Han