Abstract: A microprocessor with a variable clock operation, which is operative at a highest speed as well as a lowest speed, within a maximum performance range of the microprocessor is disclosed. The invention includes a microprocessor having a Critical Path Operation (CPO) block that is operative at a speed corresponding to an external clock signal; a decision circuit for deciding an operation state of the microprocessor, according to a test result of the CPO block in the microprocessor; a MUX unit for selecting a signal from either a signal from the decision circuit or an external signal, selecting a signal intended to control, and forwarding the selected signal; a controlling unit for receiving a signal from the MUX unit for providing a control signal for varying a clock signal; and a PLL circuit for varying the clock signal in response to the control signal from the controlling unit for applying a varied clock signal to the microprocessor.