Abstract: A printed circuit board includes a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on the plurality of first insulating layers, and a plurality of first adhesive layers respectively disposed between the plurality of first insulating layers to respectively cover the plurality of first wiring layers; and a second substrate portion disposed on the first substrate portion, and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on the plurality of second insulating layers, and a plurality of second adhesive layers respectively disposed between the plurality of second insulating layers to respectively cover the plurality of second wiring layers.

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

Abstract: Provided are semiconductor devices. The semiconductor device includes a substrate, a gate structure disposed on the substrate and extending in a first direction, and an active pattern spaced apart from the substrate in a second direction, extending in a third direction, and penetrating the gate structure, wherein the active pattern includes a two-dimensional material, the gate structure comprises a gate insulating layer, a lower gate conductive layer, a ferroelectric layer, and an upper gate conductive layer, which are sequentially stacked on the active pattern, the gate insulating layer includes hexagonal boron nitride (h-BN), and the ferroelectric layer includes a bilayer of a two-dimensional material.

Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

Abstract: A semiconductor device including a ferroelectric field effect transistor (FeFET) and a method for fabricating the same are provided. The semiconductor device includes a substrate, a gate electrode film including a metal element, on the substrate, a gate insulating film including a ferroelectric material between the substrate and the gate electrode film, and a buffer oxide film including an oxide of a semiconductor material between the gate insulating film and the gate electrode film, the buffer oxide film being in contact with the gate insulating film.

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first active pattern extending in a first direction; a second active pattern spaced apart extending in the first direction, the first active pattern being provided between the second active pattern and a substrate; a gate structure extending in a second direction, the first active pattern and the second active pattern passing through the gate structure, and the second direction crossing the first direction; a first source/drain area connected with the first active pattern and provided on a side of the gate structure; a second source/drain area connected with the second active pattern and provided on the first source/drain area; a first insulating structure provided between the substrate and the first source/drain area, the first insulating structure not being provided between the substrate and the gate structure; and a second insulating structure provided between the first source/drain area and the second source/drain area.

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

Abstract: A semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a substrate, a first lower wire pattern and a first upper wire pattern stacked on the substrate, and spaced apart from each other; a second lower wire pattern and a second upper wire pattern stacked on the substrate, spaced apart from each other, and spaced apart from the first lower and upper wire patterns; a first gate line surrounding the first lower wire pattern and the first upper wire pattern; a second gate line surrounding the second lower wire pattern and the second upper wire pattern and spaced apart from the first gate line; a first lower source/drain area; a first upper source/drain area; and a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other.

Abstract: A semiconductor device comprises a substrate, a first active pattern on the substrate and extending in a first direction, a second active pattern extending in the first direction spaced apart from the substrate, a gate electrode extending in a second direction surrounding the first and second active patterns, and a high dielectric film between the first and second active patterns and the gate electrode. The gate electrode includes first and second work function adjusting films surrounding the high dielectric film on the first and second active patterns, and a filling conductive film surrounding the first and second work function adjusting films. The first and second work function adjusting films include first and second work function conductive films, each of which includes a first metal film. A thickness of the first metal film of the first work function conductive film is greater than that of the second work function conductive film.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on the substrate, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, a source/drain region on at least one side of the gate electrode, a source/drain contact extending into the source/drain region and including a filling layer and a barrier layer along a sidewall of the filling layer, and a silicide layer between the source/drain region and the filling layer, the silicide layer including a first sidewall in contact with the filling layer and a second sidewall in contact with the source/drain region, wherein the barrier layer is not between the filling layer and the source/drain region.