Patents by Inventor Dae Won HWANG

Dae Won HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11056595
    Abstract: A semiconductor device includes a substrate, a counter-doping region, and a Schottky barrier diode (SBD) in which a breakdown voltage is improved by using counter doping, and a manufacturing method thereof. A breakdown voltage may be improved by lowering a concentration of impurity on the region and enhancing the characteristics of the semiconductor device including the SBD.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: July 6, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Yong Won Lee, Jin Woo Han, Dae Won Hwang, Kyung Wook Kim
  • Publication number: 20190198682
    Abstract: A semiconductor device includes a substrate, a counter-doping region, and a Schottky barrier diode (SBD) in which a breakdown voltage is improved by using counter doping, and a manufacturing method thereof. A breakdown voltage may be improved by lowering a concentration of impurity on the region and enhancing the characteristics of the semiconductor device including the SBD.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Yong Won LEE, Jin Woo HAN, Dae Won HWANG, Kyung Wook KIM
  • Patent number: 10269988
    Abstract: A semiconductor device includes a substrate, a counter-doping region, and a Schottky barrier diode (SBD) in which a breakdown voltage is improved by using counter doping, and a manufacturing method thereof. A breakdown voltage may be improved by lowering a concentration of impurity on the region and enhancing the characteristics of the semiconductor device including the SBD.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: April 23, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Yong Won Lee, Jin Woo Han, Dae Won Hwang, Kyung Wook Kim
  • Patent number: 10038056
    Abstract: A method for fabricating a semiconductor device is disclosed. A plurality of trenches is formed at a predetermined cell pitch in an upper surface portion of a substrate. A first insulation film is formed on the substrate. A gate electrode is formed and partially filled within each trench. A first conductivity type region is formed in the upper surface portion of the substrate between the trenches. A second conductivity type region is formed in a side surface of the substrate between the trenches and the first conductivity type region. A second insulation film is formed covering the gate electrode within each trench, wherein an upper surface of the second insulation film is positioned lower than an upper surface of the substrate. A source metal layer is formed on the second insulation film and electrically connected to the first conductivity type region and the second conductivity type region.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: July 31, 2018
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Soo Chang Kang, Seung Hyun Kim, Dae Won Hwang, Yong Won Lee
  • Publication number: 20170194433
    Abstract: A method for fabricating a semiconductor device is disclosed. A plurality of trenches is formed at a predetermined cell pitch in an upper surface portion of a substrate. A first insulation film is formed on the substrate. A gate electrode is formed within each trench, wherein the gate electrode partially fills each trench. A first conductivity type region is formed in the upper surface portion of the substrate between the trenches. A second conductivity type region is formed in a side surface of the substrate between the trenches and the first conductivity type region. A second insulation film is formed covering the gate electrode within each trench, wherein an upper surface of the second insulation film is positioned lower than an upper surface of the substrate. A source metal layer is formed on the second insulation film. The source metal layer is electrically connected to the first conductivity type region and the second conductivity type region.
    Type: Application
    Filed: December 12, 2016
    Publication date: July 6, 2017
    Inventors: Soo Chang KANG, Seung Hyun KIM, Dae Won HWANG, Yong Won LEE
  • Publication number: 20150123235
    Abstract: A semiconductor device includes a substrate, a counter-doping region, and a Schottky barrier diode (SBD) in which a breakdown voltage is improved by using counter doping, and a manufacturing method thereof. A breakdown voltage may be improved by lowering a concentration of impurity on the region and enhancing the characteristics of the semiconductor device including the SBD.
    Type: Application
    Filed: June 25, 2014
    Publication date: May 7, 2015
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Yong Won LEE, Jin Woo HAN, Dae Won HWANG, Kyung Wook KIM