Patents by Inventor Dae Woo
Dae Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12381488Abstract: An embodiment vehicle includes a DC/DC converter having a first power terminal connected to a first electrode of a first battery, a second power terminal connected to a first electrode of a second battery, and a load terminal connected to a first end of an electric load, and including a switching circuit, a transformer, and a rectifier circuit, and a controller configured to set an operation mode of the DC/DC converter to a low-voltage DC/DC converter (LDC) mode or a state-of-charge (SOC) balancing mode, wherein the DC/DC converter is configured to step down a voltage of the first power terminal through the switching circuit, the transformer, and the rectifier circuit and output the voltage to the load terminal when the LDC mode is performed and to control power transfer between the first and second power terminals through the switching circuit when the SOC balancing mode is performed.Type: GrantFiled: April 14, 2023Date of Patent: August 5, 2025Assignees: Hyundai Motor Company, Kia CorporationInventors: Tae Jong Ha, Jun Young Lee, Dae Woo Lee, Byung Gu Kang
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Patent number: 12371524Abstract: The present invention relates to a method for producing a diene-based graft copolymer resin, and a diene-based graft copolymer resin produced therefrom, the method including: mixing an aromatic vinyl-based monomer, a diene-based rubber polymer, and a polymerization initiator to prepare a first reactant; mixing a vinyl cyan-based monomer and an antioxidant to prepare a second reactant; adding and polymerizing the first reactant and the second reactant into a polymerization reactor to prepare a polymer; and removing unreacted monomers in a devolatilization tank.Type: GrantFiled: October 6, 2020Date of Patent: July 29, 2025Assignee: LG CHEM, LTD.Inventors: Jae Bum Seo, Dae Woo Lee, Jung Tae Park, Gyu Sun Kim, Ji Uk Jang
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Publication number: 20250229310Abstract: Provided are an ultrathick steel material having excellent strength and low-temperature impact toughness for flanges and a method for manufacturing same. The steel material of the present disclosure comprises, by wt %, C: 0.05-0.2%, Si: 0.05-0.5%, Mn: 1.0-2.0%, Al: 0.005-0.1%, P: 0.01% or less, S: 0.015% or less, Nb: 0.001-0.07%, V: 0.001-0.3%, Ti: 0.001-0.03%, Cr: 0.01-0.3%, Mo: 0.01-0.12%, Cu: 0.01-0.6%, Ni: 0.05-1.0%, Ca: 0.0005-0.004%, and the balance of Fe and inevitable impurities, has Ceq satisfying the range of 0.35-0.55 as calculated by the following equation, has an average ferrite grain size of 25 ?m or less in the central portion thereof, and contains a microstructure including 5-30 area % of pearlite and the balance of ferrite.Type: ApplicationFiled: December 19, 2022Publication date: July 17, 2025Applicant: POSCO Co., LtdInventor: Dae-Woo KIM
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Publication number: 20250202346Abstract: A power factor correction (PFC) circuit switching method can include coupling a PFC circuit and AC power to enable a controller to perform an initial charging operation on an output capacitor to firstly increase an output capacitor voltage, enabling the controller to secondly increase the output capacitor voltage in response to whether the firstly-increased output capacitor voltage reaches a first preset reference voltage, and enabling the controller to switch first and second poles configured in the PFC circuit at different duty ratios in response to whether the secondly-increased output capacitor voltage reaches a second preset reference voltage.Type: ApplicationFiled: September 12, 2024Publication date: June 19, 2025Inventors: Ye-Rin Lee, Dae-Woo Lee, Ki-Sang Lee, Ji-Han Lee, Youn-Sik Lee, Sang-Yun Lee, Won-Jun Kim, Geun-Ho Jang, Ye-Ji Hyeon, Seong-Wook Jeong, Han-Shin Youn, Dong-In Lee
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Patent number: 12331373Abstract: An embodiment of the present invention provides a steel material, for a pressure vessel, comprising, in weight %, 0.06-0.25% of carbon (C), 0.05-0.50% of silicon (Si), 1.0-2.0% of manganese (Mn), 0.005-0.40% of aluminum (Al), 0.010% or less of phosphorus (P), 0.0010% or less of sulfur (S), 0.001-0.03% of niobium (Nb), 0.001-0.03% of vanadium (V), 0.001-0.03% of titanium (Ti), 0.01-0.20% of chromium (Cr), 0.05-0.15% of molybdenum (Mo), 0.01-0.50% of copper (Cu), 0.05-0.50% of nickel (Ni), 0.0005-0.0050% of magnesium (Mg), 0.0005-0.0050% of calcium (Ca), 0.0020% or less of oxygen (O), and the remainder being Fe and other unavoidable impurities. A microstructure comprises in terms of area fraction 30% or less of pearlite and the remainder being ferrite. A non-metallic inclusion contains Mg—Al—Ca—O composite oxide.Type: GrantFiled: December 24, 2018Date of Patent: June 17, 2025Assignee: POSCO CO., LTDInventors: Dae-Woo Kim, Woo-Yeol Cha
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Publication number: 20250192017Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.Type: ApplicationFiled: January 27, 2025Publication date: June 12, 2025Inventors: Dae-Woo KIM, Sujit SHARAN
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Publication number: 20250183246Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.Type: ApplicationFiled: February 13, 2025Publication date: June 5, 2025Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Cheon PARK, Dae-Woo KIM, Taehun KIM, Hyuekae LEE
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Patent number: 12322549Abstract: A capacitor component includes a body, including a dielectric layer and an internal electrode layer, and an external electrode disposed on one surface of the body. The external electrode includes a conductive base and a glass disposed in the conductive base, and the glass includes 0.01 wt % or more to 5.8 wt % or less of nitrogen (N) based on a total weight of the glass.Type: GrantFiled: April 15, 2024Date of Patent: June 3, 2025Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Woo Yoon, Su Jin Lee, Da Mi Kim, Bum Suk Kang, Seong Han Park, Jeong Ryeol Kim
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Publication number: 20250163253Abstract: The present invention provides a tire tread rubber composition with improved braking performance on wet road surfaces while maintaining snow braking performance in hot-summer or cold-winter area. The tire tread rubber composition may include SBR having excellent low-temperature properties and a hydrogenated hydrocarbon resin to improve wet braking, snow braking and wear performances, and a specific vulcanizing agent to supplement wear/RR performances.Type: ApplicationFiled: August 29, 2024Publication date: May 22, 2025Inventors: Jin Oh MAENG, Donghwan PARK, Dae Woo LEE
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Publication number: 20250145047Abstract: The present invention relates to an operating system for a battery exchange station and an operating method for a battery exchange station by using same. The operating system for a battery exchange station, according to an embodiment of the present invention, comprises: a plurality of battery exchange stations; a terminal on which a dedicated application is installed, and which receives an application and service information, input from a user, for a delivery service that performs battery delivery between the plurality of battery exchange stations; and an operating server which communicates with the plurality of battery exchange stations and the terminal, wherein the operating server may determine an arrival station for the battery delivery on the basis of a degree of battery exchange congestion determined for each of the plurality of battery exchange stations.Type: ApplicationFiled: October 28, 2022Publication date: May 8, 2025Inventors: Sil Lo Jin, Ho Kyung Kim, Nam Chul Paik, In Jae Kwak, Dae Woo Kim, Sang Hwan Oh, Sang Hoon Kim, Hyeong Tae Noh, Se Hee Byun
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Patent number: 12291586Abstract: The present invention relates to a method of preparing a polymer, which includes: adding a first reaction solution including an aqueous solvent and a monomer mixture including an alkyl-substituted aromatic vinyl-based monomer, an alkyl-unsubstituted aromatic vinyl-based monomer, and a vinyl cyanide-based monomer to a reactor and initiating polymerization; and performing polymerization by continuously adding an alkyl-substituted aromatic vinyl-based monomer to the reactor, wherein the first reaction solution satisfies Expression 1 (see the description of the invention).Type: GrantFiled: November 25, 2021Date of Patent: May 6, 2025Assignee: LG CHEM, LTD.Inventors: Sung Won Hong, Hyung Sub Lee, Dae Woo Lee, Min Cheol Ju, Seong Jae Shin, Min Seung Shin, In Soo Kim
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Patent number: 12286490Abstract: Provided is a polymer production method including: batch-adding a reaction solution including a monomer mixture including a maleimide-based monomer, a vinyl aromatic monomer, and a vinyl cyanide-based monomer and an aqueous solvent to a reactor and initiating polymerization; and carrying out the polymerization while continuously adding the maleimide-based monomer and the aqueous solvent to the reactor, wherein the reaction solution satisfies the above Formula 1.Type: GrantFiled: October 18, 2021Date of Patent: April 29, 2025Assignee: LG CHEM, LTD.Inventors: In Soo Kim, Hyung Sub Lee, Dae Woo Lee, Min Cheol Ju, Min Seung Shin, Sung Won Hong
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Patent number: 12261164Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.Type: GrantFiled: October 3, 2023Date of Patent: March 25, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Cheon Park, Dae-Woo Kim, Taehun Kim, Hyuekjae Lee
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Patent number: 12258434Abstract: The present disclosure relates to an expanded foam solution for forming a thermosetting expanded foam having excellent flame retardancy produced using the same. According to the present disclosure, nanoclay is mixed with a polyol-based compound using ultrasonic waves, an isocyanate-based compound is added, and a trimerization catalyst or an isocyanurate compound is mixed with the polyol-based compound so that an isocyanurate structure is formed.Type: GrantFiled: June 16, 2023Date of Patent: March 25, 2025Assignee: KYUNG DONG ONE CORPORATIONInventors: Jong Hyun Yoon, Sang Yun Lee, Dae Woo Nam
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Publication number: 20250079252Abstract: Provided is an insulation sheet for a chip on film. An insulation sheet for a chip on film according to one embodiment of the present invention is provided on the opposite surface of a printed circuit film from the surface on which a display driver IC (DDI) is mounted, and is for preventing heat generated from the display driver IC from being transferred in a direction perpendicular to the opposite surface. Accordingly, the insulation sheet for a chip on film is advantageous for lowering the temperature of the display driver IC while minimizing the transfer of received heat toward a display device housing. Moreover, due to the excellent flexibility of the insulation sheet, peeling can be prevented even when the insulation sheet is attached to a printed circuit film that is curved.Type: ApplicationFiled: September 28, 2021Publication date: March 6, 2025Inventors: In Yong SEO, Dae Woo SON, Jae Hyung SEO, Jong Eun KIM, Jong Soo KIM
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Patent number: 12239958Abstract: This invention relates to a superabsorbent polymer composition and a method for preparing the superabsorbent polymer composition. According to the present disclosure, there are provided a superabsorbent polymer composition that can exhibit a rapid absorption time without using a blowing agent, and a method for preparing the superabsorbent polymer composition.Type: GrantFiled: September 29, 2020Date of Patent: March 4, 2025Assignee: LG Chem, Ltd.Inventors: Dae Woo Nam, Jin Seok Seo, Sujin Kim
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Patent number: 12243812Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.Type: GrantFiled: November 3, 2023Date of Patent: March 4, 2025Assignee: Intel CorporationInventors: Dae-Woo Kim, Sujit Sharan
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Publication number: 20250066925Abstract: A method of manufacturing interior parts for a vehicle includes: forming a first plating layer on a surface of an injection molded product through electroless plating; printing a symbol part on the first plating layer; partially removing the first plating layer to a size corresponding to the symbol part from a rear surface of the injection molded product; forming a second plating layer on the first plating layer; and removing the symbol part and the first plating layer from the surface of the injection molded product on which the second plating layer is formed.Type: ApplicationFiled: December 15, 2023Publication date: February 27, 2025Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, BS TECHNICS CO.,LTD., ALPS ELECTRIC KOREA CO.,LTD.Inventors: Young Ju Lee, Kwang Pyo Cho, Hong Sik Chang, Seung Sik Han, Young Jai Im, Jun Sik Kim, Young Do Kim, Jung Sik Choi, Tae Kyoung Jung, In Ho Park, Seon Dong Kim, Dae Woo Park
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Publication number: 20250070056Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Inventors: Dae-Woo KIM, Sujit SHARAN, Sairam AGRAHARAM
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Patent number: 12237308Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.Type: GrantFiled: December 29, 2023Date of Patent: February 25, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuekjae Lee, Dae-Woo Kim, Eunseok Song