Abstract: Discussed is a welding inspection apparatus for battery modules capable of applying an alternating current to a bank constituted by two or more battery cells connected in parallel and a battery module constituted by one or more banks connected in series to calculate an impedance and a resistance value of each of the one or more banks, and a method of inspecting welding of the battery module using the welding inspection apparatus.

Abstract: Provided is a semiconductor package including a substrate and a semiconductor chip formed on the substrate. The semiconductor chip may include a chip alignment mark on a surface of the semiconductor chip, and wiring patterns formed on a surface of the substrate, wherein the chip alignment mark is bonded to the wiring patterns. Accordingly, the surface area of the semiconductor chip may be reduced.

Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads include first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.

Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.

Abstract: A semiconductor chip for a tape automated bonding (TAB) package is disclosed. The semiconductor chip comprises a connection surface including a set of input pads connected to internal circuitry of the chip and for conveying external signals to the internal circuitry, the set of input pads comprising all of the input pads on the chip. The connection surface includes a set of output pads connected to internal circuitry of the chip and for conveying internal chip signals to outside the chip, the set of output pads comprising all of the output pads on the chip.

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract: A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area.

Abstract: A semiconductor chip for a tape automated bonding (TAB) package is disclosed. The semiconductor chip comprises a connection surface including a set of input pads connected to internal circuitry of the chip and for conveying external signals to the internal circuitry, the set of input pads comprising all of the input pads on the chip. The connection surface includes a set of output pads connected to internal circuitry of the chip and for conveying internal chip signals to outside the chip, the set of output pads comprising all of the output pads on the chip. The connection surface includes a first edge and a second edge that are substantially parallel to each other and are opposite each other on a respective first side and second side of the chip, and a third edge and fourth edge that are substantially perpendicular to the first and second edges, and are opposite each other on a respective third side and fourth side of the chip.

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract: Provided is a semiconductor package including a substrate and a semiconductor chip formed on the substrate. The semiconductor chip may include a chip alignment mark on a surface of the semiconductor chip, and wiring patterns formed on a surface of the substrate, wherein the chip alignment mark is bonded to the wiring patterns. Accordingly, the surface area of the semiconductor chip may be reduced.

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract: A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.

Abstract: A semiconductor chip package includes an IC chip and a tape circuit substrate. The tape circuit substrate has a base film and a plurality of beam leads formed on the base film. One end portion of each beam lead extends from the base film, and the extended portion has a widthwise wavy portion. The widthwise wavy portion may be, for example, semicircular shaped, S-shaped or zig-zag shaped. The IC chip has chip pads formed on a top surface thereof.

Abstract: A bonding apparatus and method thereof to bond the bonding portions of an FPC cable to pads of a print head die in order to electrically connect the print head die of an ink jet print head assembly include a stage and a bonding tool. The print head die includes resistive heaters, signal lines connected to the resistive heaters, and electrical pads to connect the signal lines to an outside of the print head die to the FPC cable having conductors having bonding portions facing the pads. The print head die is supported on the stage with the pads facing upward. The bonding tool includes a tip that press bonding portions of the FPC cable against corresponding pads of the print head die placed on the stage, and heats the bonding portions in contact with the pads to bond the bonding portion to the pads.

Abstract: A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.

Abstract: A tape circuit board for manufacturing a fine pitch semiconductor chip package, a method for manufacturing the tape circuit board, and a semiconductor chip package using the tape circuit board are provided. The tape circuit board includes an insulating base film having a first surface and a second surface. An adhesive layer is formed on the first surface of the base film. Further, wiring patterns are formed on the adhesive layer. Conductive bumps extend through the base film and the adhesive layer and are connected to the wiring patterns. The conductive bumps extend above the second surface of the base film.

Abstract: A semiconductor chip package includes an IC chip and a tape circuit substrate. The tape circuit substrate has a base film and a plurality of beam leads formed on the base film. One end portion of each beam lead extends from the base film, and the extended portion has a wavy portion. The wavy portion can be, for example, semicircular shaped, an S-shaped, or a zigzag shaped. The IC chip has chip pads formed on a top surface thereof. The beam lead is bonded to the chip pad through an inner lead bonding (ILB) process. During the ILB process, the wavy portion disperses the stress produced in the beam lead. Therefore, a crack or a break of the beam lead due to the stress can be effectively prevented, improving interconnection reliability between the IC chip and the tape circuit substrate.

Abstract: A tape circuit board for manufacturing a fine pitch semiconductor chip package, a method for manufacturing the tape circuit board, and a semiconductor chip package using the tape circuit board are provided. The tape circuit board includes an insulating base film having a first surface and a second surface. An adhesive layer is formed on the first surface of the base film. Further, wiring patterns are formed on the adhesive layer. Conductive bumps extend through the base film and the adhesive layer and are connected to the wiring patterns. The conductive bumps extend above the second surface of the base film.

Abstract: A tape circuit board for manufacturing a fine pitch semiconductor chip package, a method for manufacturing the tape circuit board, and a semiconductor chip package using the tape circuit board are provided. The tape circuit board includes an insulating base film having a first surface and a second surface. An adhesive layer is formed on the first surface of the base film. Further, wiring patterns are formed on the adhesive layer. Conductive bumps extend through the base film and the adhesive layer and are connected to the wiring patterns. The conductive bumps extend above the second surface of the base film.