Patents by Inventor Dae-woong Kwon
Dae-woong Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240158338Abstract: A novel compound for a capping layer, and an organic light-emitting device containing the same are disclosed.Type: ApplicationFiled: December 29, 2023Publication date: May 16, 2024Inventors: Ho Wan HAM, Hyun Cheol AN, Hee Joo KIM, Dong Jun KIM, Ja Eun ANN, Dong Yuel KWON, Sung Kyu LEE, Hwan Il JE, Bo Ra LEE, Yeong Rong PARK, Il Soo OH, Dae Woong LEE, Hyeon Jeong IM, Ill Hun CHO
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Publication number: 20240164138Abstract: A novel compound for a capping layer, and an organic light-emitting device containing the same are disclosed.Type: ApplicationFiled: December 29, 2023Publication date: May 16, 2024Inventors: Ho Wan HAM, Hyun Cheol AN, Hee Joo KIM, Dong Jun KIM, Ja Eun ANN, Dong Yuel KWON, Sung Kyu LEE, Tae Jin LEE, Bo Ra LEE, Yeong Rong PARK, Il Soo OH, Dae Woong LEE, Hyeon Jeong IM, Ill Hun CHO
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Publication number: 20240037381Abstract: According to one aspect of the present invention, a ternary neural network accelerator device includes a first semiconductor device comprising a first source terminal, a first drain terminal, and a first gate terminal, a second semiconductor device comprising a second source terminal, a second drain terminal, and a second gate terminal, a first searching line connected to the first drain terminal, a second searching line connected to the second drain terminal, and a matching line commonly connected to the first source terminal and the second source terminal, wherein ternary weight and ternary input are each set by either of a first operation and a second operation and nine computation results are output through the matching line according to conditions of the ternary weight and ternary input.Type: ApplicationFiled: April 20, 2023Publication date: February 1, 2024Applicant: Inha University Research and Business FoundationInventors: Yeongkyo SEO, Dae Woong KWON
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Patent number: 10074435Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectioType: GrantFiled: March 8, 2018Date of Patent: September 11, 2018Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Byung Gook Park, Dae Woong Kwon, Do Bin Kim, Sang Ho Lee
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Publication number: 20180197615Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectioType: ApplicationFiled: March 8, 2018Publication date: July 12, 2018Inventors: Byung Gook PARK, Dae Woong KWON, Do Bin KIM, Sang Ho LEE
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Patent number: 9947413Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectioType: GrantFiled: November 3, 2016Date of Patent: April 17, 2018Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Byung Gook Park, Dae Woong Kwon, Do Bin Kim, Sang Ho Lee
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Patent number: 9824759Abstract: In a method of programming a non-volatile memory device, a first voltage is applied to a selected memory cell for programming, and a second voltage is applied to a non-selected memory cell. Before the second voltage rises to a predetermined voltage level, which is less than a program voltage level, the first voltage is greater than the second voltage or the second voltage is maintained at greater than a ground voltage level. Related non-volatile memory devices and memory systems are also discussed.Type: GrantFiled: January 29, 2015Date of Patent: November 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-woong Kwon, Jai-hyuk Song, Chang-sub Lee
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Patent number: 9754673Abstract: A method of controlling a 3D non-volatile memory device includes initially leveling threshold voltages of the string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level; applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer selected among the plurality of memory layers comprising the initially leveled string selection transistors; and setting threshold voltages of the initially leveled string selection transistors in the first memory layer by controlling each of the plurality of string selection lines respectively coupled with the initially leveled string selection transistors during the first time varying section of the first time varying erase voltage signal.Type: GrantFiled: November 2, 2016Date of Patent: September 5, 2017Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Byung Gook Park, Dae Woong Kwon, Do Bin Kim, Sang Ho Lee
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Patent number: 9685235Abstract: A 3D non-volatile memory device may include a dummy string selection line, string selection lines, wordlines, bitlines, a ground selection line, and memory layers. Each of the memory layers comprising channel lines respectively coupled to the bitlines via first ends and coupled to a common source line of the memory layer via second ends. The dummy string selection line, the string selection lines, the wordlines, and the ground selection line intersect with the channel lines, and each of the channel lines defines a memory string. Initializing the 3D non-volatile memory device may include programming string selection transistors coupled with the string selection lines to have one or more threshold values, and programming a dummy string selection transistor coupled with the dummy string selection line to have a predetermined threshold value, such that the dummy string selection transistor together with the string selection transistors function as string selection transistors.Type: GrantFiled: November 14, 2016Date of Patent: June 20, 2017Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Byung Gook Park, Dae Woong Kwon, Do Bin Kim, Sang Ho Lee
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Publication number: 20170140829Abstract: A 3D non-volatile memory device may include a dummy string selection line, string selection lines, wordlines, bitlines, a ground selection line, and memory layers. Each of the memory layers comprising channel lines respectively coupled to the bitlines via first ends and coupled to a common source line of the memory layer via second ends. The dummy string selection line, the string selection lines, the wordlines, and the ground selection line intersect with the channel lines, and each of the channel lines defines a memory string. Initializing the 3D non-volatile memory device may include programming string selection transistors coupled with the string selection lines to have one or more threshold values, and programming a dummy string selection transistor coupled with the dummy string selection line to have a predetermined threshold value, such that the dummy string selection transistor together with the string selection transistors function as string selection transistors.Type: ApplicationFiled: November 14, 2016Publication date: May 18, 2017Inventors: Byung Gook PARK, Dae Woong KWON, Do Bin KIM, Sang Ho LEE
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Publication number: 20170133095Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectioType: ApplicationFiled: November 3, 2016Publication date: May 11, 2017Inventors: Byung Gook PARK, Dae Woong KWON, Do Bin KIM, Sang Ho LEE
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Publication number: 20170125109Abstract: A method of controlling a 3D non-volatile memory device includes initially leveling threshold voltages of the string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level; applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer selected among the plurality of memory layers comprising the initially leveled string selection transistors; and setting threshold voltages of the initially leveled string selection transistors in the first memory layer by controlling each of the plurality of string selection lines respectively coupled with the initially leveled string selection transistors during the first time varying section of the first time varying erase voltage signal.Type: ApplicationFiled: November 2, 2016Publication date: May 4, 2017Inventors: Byung Gook PARK, Dae Woong KWON, Do Bin KIM, Sang Ho LEE
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Patent number: 9123817Abstract: Example embodiments disclose transistors and electronic devices including the transistors. A transistor may include a charge blocking layer between a gate insulating layer and a gate. An energy barrier between the gate insulating layer and the gate may be increased by the charge blocking layer. The transistor may be an oxide transistor including a channel layer formed of an oxide semiconductor.Type: GrantFiled: April 28, 2011Date of Patent: September 1, 2015Assignees: Samsung Electronics Co., Ltd., SNU R&DB FoundationInventors: Dae-woong Kwon, Jae-chul Park, Byung-gook Park, Sang-wan Kim, Jang-hyun Kim, Ji-soo Chang
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Publication number: 20150228345Abstract: In a method of programming a non-volatile memory device, a first voltage is applied to a selected memory cell for programming, and a second voltage is applied to a non-selected memory cell. Before the second voltage rises to a predetermined voltage level, which is less than a program voltage level, the first voltage is greater than the second voltage or the second voltage is maintained at greater than a ground voltage level. Related non-volatile memory devices and memory systems are also discussed.Type: ApplicationFiled: January 29, 2015Publication date: August 13, 2015Inventors: Dae-woong Kwon, Jal-hyuk Song, Chang-sub Lee
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Patent number: 9105235Abstract: A method of driving an active display device. The method including recovering a threshold voltage of a switching transistor connected to a pixel. The recovering including applying a negative bias voltage to the switching transistor prior to charging each pixel during a charging period. The negative bias voltage is applied to a drain of the switching transistor.Type: GrantFiled: August 29, 2011Date of Patent: August 11, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-woong Kwon, Byung-gook Park, Chang-jung Kim, Jae-chul Park
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Publication number: 20120113078Abstract: A method of driving an active display device. The method including recovering a threshold voltage of a switching transistor connected to a pixel. The recovering including applying a negative bias voltage to the switching transistor prior to charging each pixel during a charging period. The negative bias voltage is applied to a drain of the switching transistor.Type: ApplicationFiled: August 29, 2011Publication date: May 10, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-woong Kwon, Byung-gook Park, Chang-jung Kim, Jae-chul Park
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Publication number: 20120085998Abstract: Example embodiments disclose transistors and electronic devices including the transistors. A transistor may include a charge blocking layer between a gate insulating layer and a gate. An energy barrier between the gate insulating layer and the gate may be increased by the charge blocking layer. The transistor may be an oxide transistor including a channel layer formed of an oxide semiconductor.Type: ApplicationFiled: April 28, 2011Publication date: April 12, 2012Inventors: Dae-woong Kwon, Jae-chul Park, Byung-gook Park, Sang-wan Kim, Jang-hyun Kim, Ji-soo Chang
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Patent number: D1021767Type: GrantFiled: November 9, 2021Date of Patent: April 9, 2024Assignee: LG Energy Solution, Ltd.Inventors: Hyun Beom Kim, Jeong Min Ha, Gi Man Kim, Dae Hong Kim, Sin Woong Kim, Se Young Oh, Geun Hee Kim, Hyung Ho Kwon