Patents by Inventor Daewung KANG

Daewung KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10283566
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: May 7, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jongsun Sel, Tuan Pham, Mitsuteru Mushiga, Yoshihiro Ikeda, Daewung Kang, Akio Nishida
  • Publication number: 20180350879
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.
    Type: Application
    Filed: June 1, 2017
    Publication date: December 6, 2018
    Inventors: Jongsun Sel, Tuan Pham, Mitsuteru Mushiga, Yoshihiro Ikeda, Daewung Kang, Akio Nishida
  • Patent number: 10121794
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 6, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Marika Gunji-Yoneoka, Atsushi Suyama, Jayavel Pachamuthu, Tsuyoshi Hada, Daewung Kang, Murshed Chowdhury, James Kai, Hiro Kinoshita, Tomoyuki Obu, Luckshitha Suriyasena Liyanage
  • Patent number: 10115770
    Abstract: A method is provided that includes forming a dielectric material and a first sacrificial material above a substrate, forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material, forming a first hole in the second sacrificial material, the first hole disposed in a first direction, forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole, forming a second hole in the second sacrificial material, forming a second portion of the nonvolatile memory material on a sidewall of the second hole, forming a local bit line in the second hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 30, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Jongsun Sel, Daewung Kang, Michiaki Sano, Yohei Yamada, Mitsuteru Mushiga, Tuan Pham
  • Publication number: 20180247976
    Abstract: A method is provided that includes forming a dielectric material and a first sacrificial material above a substrate, forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material, forming a first hole in the second sacrificial material, the first hole disposed in a first direction, forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole, forming a second hole in the second sacrificial material, forming a second portion of the nonvolatile memory material on a sidewall of the second hole, forming a local bit line in the second hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.
    Type: Application
    Filed: February 28, 2017
    Publication date: August 30, 2018
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Jongsun Sel, Daewung Kang, Michiaki Sano, Yohei Yamada, Mitsuteru Mushiga, Tuan Pham
  • Publication number: 20170365613
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.
    Type: Application
    Filed: September 29, 2016
    Publication date: December 21, 2017
    Inventors: Marika GUNJI-YONEOKA, Atsushi SUYAMA, Jayavel PACHAMUTHU, Tsuyoshi HADA, Daewung KANG, Murshed CHOWDHURY, James KAI, Hiro KINOSHITA, Tomoyuki OBU, Luckshitha Suriyasena LIYANAGE