Abstract: A high speed and low power D/A converter which is capable of accurately outputting an analog value and implementing a high speed operation by reducing noise and errors during the conversion. The converter includes an upper current cell plate for forming analog voltages from a 126th level to a 255th level in accordance with decoding of inputted digital values by a first column decoder and a first row decoder, a lower current cell plate for forming analog voltages from a 0th level to a 125th level in accordance with decoding of the inputted digital values by a second column decoder and second row decoder, and a multiplexer for selectively outputting the analog voltage from the upper current cell plate or the lower current cell plate in accordance with a binary bit value of a most significant bit (MSB) of the inputted digital signal.

Abstract: An improved current source cell apparatus for a digital/analog converter which is capable of off-setting noises and obtaining a faster current switching by using different type current source cells which are alternately arranged, thus being well adaptable to a high frequency digital/analog converter. First current source cells receive a first bias voltage, a second bias voltage, and an inverted second voltage, respectively, and are enabled when the second bias voltage is a low level signal. A plurality of second current source cells are connected alternatingly with the first current source cells, and also receive the first bias voltage, the second bias voltage, and the inverted second bias voltage, respectively, and are enabled when the second bias voltage is a high level signal. A load resistor is commonly connected with the output terminals of the first and second current source cells through a common node, for thus obtaining an output voltage drop thereacross as an analog signal.

Abstract: An output buffer circuit for a memory device comprising a pull-up path including first and second PMOS transistors for forming two parallel charging paths, and a pull-down path including first and second NMOS transistors for forming two parallel discharging paths. The first and second PMOS transistors are selectively operated according to a level of an output voltage at an output terminal to perform a charging operation for a load capacitance connected to the output terminal. The first and second NMOS transistors are selectively operated according to the level of the output voltage at the output terminal to perform a discharging operation for the load capacitance through a lead inductance.