Patents by Inventor Dae-Chul JEONG

Dae-Chul JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9722829
    Abstract: A pulse shaping circuit is configured to shape a waveform of an edge of a signal applied to a switch of a power amplifier included in an on-off keying transmitter.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: August 1, 2017
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Jae Sup Lee, Bum Man Kim, Han-Kyu Lee, Dae Chul Jeong, Tae Young Chung
  • Patent number: 9667241
    Abstract: A leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: May 30, 2017
    Assignees: Samsung Electronics Co., Ltd., Poshtech Academy-Industry Foundation
    Inventors: Jaesup Lee, Tae-Young Chung, Bum-Man Kim, Dae-Chul Jeong
  • Patent number: 9436202
    Abstract: A power circuit for reducing a leakage power using a negative voltage is provided. The power circuit includes a current source including a transistor including a gate. The power circuit further includes a current source control circuit connected to the gate of the transistor, and configured to apply a positive voltage to the gate of the transistor if the current source is to operate in an active mode, and apply the negative voltage to the gate of the transistor if the current source is to operate in an inactive mode.
    Type: Grant
    Filed: November 17, 2012
    Date of Patent: September 6, 2016
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Jae Sup Lee, Seong Joong Kim, Bum Man Kim, Han-Kyu Lee, Dae-Chul Jeong, Tae Young Chung
  • Publication number: 20160241229
    Abstract: A leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.
    Type: Application
    Filed: September 24, 2015
    Publication date: August 18, 2016
    Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaesup LEE, Tae-Young CHUNG, Bum-Man KIM, Dae-Chul JEONG
  • Publication number: 20150139362
    Abstract: A pulse shaping circuit is configured to shape a waveform of an edge of a signal applied to a switch of a power amplifier included in an on-off keying transmitter.
    Type: Application
    Filed: February 26, 2014
    Publication date: May 21, 2015
    Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Sup LEE, Bum Man KIM, Han-Kyu LEE, Dae Chul JEONG, Tae Young CHUNG
  • Publication number: 20130193948
    Abstract: A power circuit for reducing a leakage power using a negative voltage is provided. The power circuit includes a current source including a transistor including a gate. The power circuit further includes a current source control circuit connected to the gate of the transistor, and configured to apply a positive voltage to the gate of the transistor if the current source is to operate in an active mode, and apply the negative voltage to the gate of the transistor if the current source is to operate in an inactive mode.
    Type: Application
    Filed: November 17, 2012
    Publication date: August 1, 2013
    Inventors: Jae Sup LEE, Seong Joong KIM, Bum Man KIM, Han-Kyu LEE, Dae-Chul JEONG, Tae Young CHUNG