Abstract: Provided is a pulley structure of a belt type electric power steering (EPS) gear, and more particularly, a pulley structure of a belt type EPS gear capable of providing good assemblability using an engineering plastic and a specific structure. The pulley structure of the belt type EPS gear includes an insert ring section coupled to a ball nut, a support section configured to support the insert ring section, a first flange section configured to prevent separation of a belt, a pulley having a driving section configured to receive a driving force of the belt, a support frame disposed at one side surface of the driving section and having a bent shape to have an internal space when coupled to the ball nut, and a second flange section disposed at one side surface of the support frame and configured to prevent separation of the belt.

Abstract: Provided is a pulley structure of a belt type electric power steering (EPS) gear, and more particularly, a pulley structure of a belt type EPS gear capable of providing good assemblability using an engineering plastic and a specific structure. The pulley structure of the belt type EPS gear includes an insert ring section coupled to a ball nut, a support section configured to support the insert ring section, a first flange section configured to prevent separation of a belt, a pulley having a driving section configured to receive a driving force of the belt, a support frame disposed at one side surface of the driving section and having a bent shape to have an internal space when coupled to the ball nut, and a second flange section disposed at one side surface of the support frame and configured to prevent separation of the belt.

Abstract: A data path circuit includes a bit line sense amplifier, a local input/output line precharger connected to a local input/output line pair, a global input/output line precharger connected to a global input/output line pair, a column selector connecting a bit line pair connected to the bit line sense amplifier and the local input/output line pair to each other in response to a column selection signal, and a local input/output line selector connecting the local input/output line pair and the global input/output line pair to each other in response to a multiplexing control signal. A discharge path generator decreases the potential on the global input/output line pair down to a predetermined level in response to a data masking control signal which is activated earlier than the column selection signal during a data masking operation mode.

Abstract: Parallel bit test circuits for use in a semiconductor memory devices are provided which include a first bus that has N bus lines that are configured to transfer a first group of N bits of test result data and a second bus that has N bus lines that are configured to transfer a second group of N bits of test result data. These parallel bit test circuits further include a switching unit that has a plurality of unit switches, where each switch is configured to connect a bus line of the first bus and a respective bus line of the second bus in response to a switching control signal that is applied after the second group of N bits of test result data are output from the second bus, to transfer the first group of N bits of test result data from the first bus to the second bus so as to output a total of 2N bits of test result data through the second bus.

Abstract: A combustion fan installation structure of a gas radiation oven range is disclosed in which a combustion fan (200) is coupled at a space outside a space where a radiant burner (40) is positioned. Since the temperature of the sucked air for combustion is constantly maintained, an air with a sufficient air density can be supplied. Thus, it can have a stable combustion performance. In addition, an influence of the temperature change generated when the oven or the grill is operated can be excluded. Accordingly, a reliability of a combustion performance of the gas radiation oven range to be mainly used in kitchens or in hotels can be improved.

Abstract: According to one aspect, an on-die termination (ODT) circuit is controlled during transition from a first power mode to a second power mode of a memory device. The transition from an asynchronous ODT circuit path to a synchronous ODT circuit path is delayed to compensate for an operational latency of a delay locked loop (DLL) circuit.

Abstract: A data path circuit includes a bit line sense amplifier, a local input/output line precharger connected to a local input/output line pair, a global input/output line precharger connected to a global input/output line pair, a column selector connecting a bit line pair connected to the bit line sense amplifier and the local input/output line pair to each other in response to a column selection signal, and a local input/output line selector connecting the local input/output line pair and the global input/output line pair to each other in response to a multiplexing control signal. A discharge path generator decreases the potential on the global input/output line pair down to a predetermined level in response to a data masking control signal which is activated earlier than the column selection signal during a data masking operation mode.

Abstract: A gas radiation oven range including an outer case (10) which is formed with an upper side opened, having an internal space, a ceramic glass (20) which is covered and combined with an upper end of the outer case (10), a plurality of burner housings (300) which are combined to be contacted with a lower surface of the ceramic glass (20), forms an exhaust passage (F) with the lower surface of the ceramic glass (20), and is integrally combined with a plurality of ports with different sizes, a radiant burner (40) which is combined with a side surface of the respective burner housings (300), for generating a radiant wave, combusting mixed gas and a shared discharge unit which is positioned among the burner housings (300) and combined to be connected to respective exhaust passages (F) which are formed at a side portion of the burner housings (300).

Abstract: A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the received test pattern data to the test pattern data.

Abstract: Parallel bit test circuits for use in a semiconductor memory devices are provided which include a first bus that has N bus lines that are configured to transfer a first group of N bits of test result data and a second bus that has N bus lines that are configured to transfer a second group of N bits of test result data. These parallel bit test circuits further include a switching unit that has a plurality of unit switches, where each switch is configured to connect a bus line of the first bus and a respective bus line of the second bus in response to a switching control signal that is applied after the second group of N bits of test result data are output from the second bus, to transfer the first group of N bits of test result data from the first bus to the second bus so as to output a total of 2N bits of test result data through the second bus.

Abstract: According to one aspect, an on-die termination (ODT) circuit is controlled during transition from a first power mode to a second power mode of a memory device. The transition from an asynchronous ODT circuit path to a synchronous ODT circuit path is delayed to compensate for an operational latency of a delay locked loop (DLL) circuit.

Abstract: Provided are a semiconductor memory device having a wordline enable signal line arrangement scheme, which can reduce VPP power consumption and can increase the speed of driving a sub-wordline, and a method of arranging wordline enable signal lines in the semiconductor memory device. In the semiconductor memory device, a wordline enable driver is arranged in a row decoder region outside a memory array region, and the wordline enable signal lines are formed of an uppermost metal layer among three metal layers constituting the semiconductor memory device. Each of the wordline enable signal lines is connected to a sub-wordline driver, rather than to a pair of sub-wordline drivers. In other words, the wordline enable signal lines vertically and horizontally extend forming an inverse L shape.

Abstract: A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the received test pattern data to the test pattern data.

Abstract: Provided are a semiconductor memory device having a wordline enable signal line arrangement scheme, which can reduce VPP power consumption and can increase the speed of driving a sub-wordline, and a method of arranging wordline enable signal lines in the semiconductor memory device. In the semiconductor memory device, a wordline enable driver is arranged in a row decoder region outside a memory array region, and the wordline enable signal lines are formed of an uppermost metal layer among three metal layers constituting the semiconductor memory device. Each of the wordline enable signal lines is connected to a sub-wordline driver, rather than to a pair of sub-wordline drivers. In other words, the wordline enable signal lines vertically and horizontally extend forming an inverse L shape.

Abstract: An integrated circuit memory device includes a memory cell array, a plurality of data input lines configured to convey data to the memory cell array and a plurality of data output lines configured to convey data from the memory cell array. The device also includes a memory write buffer that receives write data for the memory cell array and responsively drives the data input lines, a sense amplifier and a plurality of sense amplifier input lines configured to convey data to the sense amplifier. The device further includes a selecting circuit coupled to the data input lines, to the data output lines and to the sense amplifier input lines and configured to selectively couple the data input lines to the sense amplifier input lines responsive to a control signal.

Abstract: A combustion fan installation structure of a gas radiation oven range is disclosed in which a combustion fan (200) is coupled at a space outside a space where a radiant burner (40) is positioned. Since the temperature of the sucked air for combustion is constantly maintained, an air with a sufficient air density can be supplied. Thus, it can have a stable combustion performance. In addition, an influence of the temperature change generated when the oven or the grill is operated can be excluded. Accordingly, a reliability of a combustion performance of the gas radiation oven range to be mainly used in kitchens or in hotels can be improved.

Abstract: A gas radiation oven range including an outer case (10) which is formed with an upper side opened, having an internal space, a ceramic glass (20) which is covered and combined with an upper end of the outer case (10), a plurality of burner housings (300) which are combined to be contacted with a lower surface of the ceramic glass (20), forms an exhaust passage (F) with the lower surface of the ceramic glass (20), and is integrally combined with a plurality of ports with different sizes, a radiant burner (40) which is combined with a side surface of the respective burner housings (300), for generating a radiant wave, combusting mixed gas and a shared discharge unit which is positioned among the burner housings (300) and combined to be connected to respective exhaust passages (F) which are formed at a side portion of the burner housings (300).

Abstract: An integrated circuit memory device includes a memory cell array, a plurality of data input lines configured to convey data to the memory cell array and a plurality of data output lines configured to convey data from the memory cell array. The device also includes a memory write buffer that receives write data for the memory cell array and responsively drives the data input lines, a sense amplifier and a plurality of sense amplifier input lines configured to convey data to the sense amplifier. The device further includes a selecting circuit coupled to the data input lines, to the data output lines and to the sense amplifier input lines and configured to selectively couple the data input lines to the sense amplifier input lines responsive to a control signal.