Patents by Inventor Dae Hee Weon

Dae Hee Weon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6544822
    Abstract: A method for fabricating a MOSFET device having a metal gate with an ultra shallow junction and allowing the application of a self-aligned contact. A sacrificial gate is formed on a silicon substrate, as is a first silicon epitaxial layer, which is thinner than the sacrificial gate. Elevated source/drain regions are formed on the silicon substrate by implanting desired impurity ions. An interlayer insulating film is deposited over the resultant structure and polished to expose the sacrificial gate. A groove is formed in which a gate insulating film and a metal film are deposited. The metal film, the gate insulating film and the interlayer insulating film are polished until the first silicon epitaxial layer is exposed. A second silicon epitaxial layer is then formed on the first silicon epitaxial layer.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: April 8, 2003
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Tae Kyun Kim, Dae Hee Weon
  • Patent number: 6472303
    Abstract: A method of manufacturing a semiconductor device having the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a selective silicon layer in the contact hole, and forming a selective conductive plug on the selective silicon layer.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: October 29, 2002
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dae Hee Weon, Seok Kiu Lee
  • Patent number: 6368925
    Abstract: An epi-channel of a uniform shape is formed by adjusting the temperature and pressure of H2 bake process to prevent the etching of a separation oxide at an interface of an active region and a field region thereby ensuring that an epi-channel is formed having a uniform shape.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: April 9, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Dae Hee Weon, Seung Ho Hahn
  • Publication number: 20020001891
    Abstract: Disclosed is a method for fabricating a MOSFET device (and the MOSFET device itself) having a metal gate capable of forming an ultra shallow junction and allowing application of a self-aligned contact as a following process.
    Type: Application
    Filed: June 20, 2001
    Publication date: January 3, 2002
    Inventors: Tae Kyun Kim, Dae Hee Weon
  • Publication number: 20020001907
    Abstract: An epi-channel of a uniform shape is formed by adjusting the temperature and pressure of H2 bake process to prevent the etching of a separation oxide at an interface of an active region and a field region thereby ensuring that an epi-channel is formed having a uniform shape.
    Type: Application
    Filed: June 15, 2001
    Publication date: January 3, 2002
    Inventors: Dae Hee Weon, Seung Ho Hahn
  • Patent number: RE45232
    Abstract: A method of manufacturing a semiconductor device having the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a selective silicon layer in the contact hole, and forming a selective conductive plug on the selective silicon layer.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: November 4, 2014
    Assignee: Conversant IP N.B. 868 Inc.
    Inventors: Dae Hee Weon, Seok Kiu Lee