Abstract: In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. A second gate structure is formed on the substrate, and has a second end portion opposite to the first end portion of the first gate structure in a diagonal direction. A cross-coupling pattern is formed between the first and second gate structure, and electrically connects the first and second gate structures to each other. A first contact plug directly contacts an upper portion of the first end portion of the first gate structure and a first upper sidewall of the cross-coupling pattern. A second contact plug directly contacts an upper portion of the second end portion of the second gate structure and a second upper sidewall of the cross-coupling pattern. In the semiconductor device, a parasitic capacitance due to the cross-coupling structure may decrease.

Abstract: In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. A second gate structure is formed on the substrate, and has a second end portion opposite to the first end portion of the first gate structure in a diagonal direction. A cross-coupling pattern is formed between the first and second gate structure, and electrically connects the first and second gate structures to each other. A first contact plug directly contacts an upper portion of the first end portion of the first gate structure and a first upper sidewall of the cross-coupling pattern. A second contact plug directly contacts an upper portion of the second end portion of the second gate structure and a second upper sidewall of the cross-coupling pattern. In the semiconductor device, a parasitic capacitance due to the cross-coupling structure may decrease.

Abstract: A semiconductor device includes a transistor formed on a substrate and including a gate electrode and a source/drain, an interlayer insulating layer covering the transistor, a first contact hole formed in the interlayer insulating layer to expose a part of the transistor, a first barrier metal conformally formed on an inner surface of the first contact hole, a first conductive layer formed on the first barrier metal to fill the first contact hole, a second contact hole formed on the first conductive layer in the interlayer insulating layer and having a larger width than the first contact hole, a second barrier metal conformally formed on an inner surface of the second contact hole, and a second conductive layer formed on the second barrier metal to fill the second contact hole, wherein the second barrier metal is formed between the first conductive layer and the second conductive layer.

Abstract: A stressed metal technology may fabricate high-Q, three-dimensional microelectronic inductors and transformers. The fabrication method may allow the production of inductors and transformers on high-resistivity silicon substrate and with metal deposition of Au and Cr that is fully compatible with semiconductor fabrication technologies. The produced inductors and transformers exhibit Q factors>60 at frequencies of 3 to 7 GHz. High efficiency, high-Q transformers with coupling factors 0.6<k<0.9 may be created with very high self-resonance frequencies.

Abstract: A stressed metal technology may fabricate high-Q, three-dimensional microelectronic inductors and transformers. The fabrication method may allow the production of inductors and transformers on high-resistivity silicon substrate and with metal deposition of Au and Cr that is fully compatible with semiconductor fabrication technologies. The produced inductors and transformers exhibit Q factors>60 at frequencies of 3 to 7 GHz. High efficiency, high-Q transformers with coupling factors 0.6<k<0.

Abstract: A method for fabricating a semiconductor device suitable for embodying an isotropic etching profile in etching a silicon substrate when a single drain cell is formed, including the steps of: a) forming a gate electrode on a silicon substrate; b) forming a spacer contacting both sides of the gate electrode; c) growing a silicon germanium layer on the silicon substrate exposed at the bottom of the spacer; d) exposing a source/drain formation region by selectively removing the silicon germanium layer; and e) growing an epitaxial silicon layer doped on the opened source/drain region.

Abstract: A method for fabricating a semiconductor device suitable for embodying an isotropic etching profile in etching a silicon substrate when a single drain cell is formed, including the steps of: a) forming a gate electrode on a silicon substrate; b) forming a spacer contacting both sides of the gate electrode; c) growing a silicon germanium layer on the silicon substrate exposed at the bottom of the spacer; d) exposing a source/drain formation region by selectively removing the silicon germanium layer; and e) growing an epitaxial silicon layer doped on the opened source/drain region.

Abstract: A method for fabricating a MOSFET device having a metal gate with an ultra shallow junction and allowing the application of a self-aligned contact. A sacrificial gate is formed on a silicon substrate, as is a first silicon epitaxial layer, which is thinner than the sacrificial gate. Elevated source/drain regions are formed on the silicon substrate by implanting desired impurity ions. An interlayer insulating film is deposited over the resultant structure and polished to expose the sacrificial gate. A groove is formed in which a gate insulating film and a metal film are deposited. The metal film, the gate insulating film and the interlayer insulating film are polished until the first silicon epitaxial layer is exposed. A second silicon epitaxial layer is then formed on the first silicon epitaxial layer.

Abstract: A method of manufacturing a semiconductor device having the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a selective silicon layer in the contact hole, and forming a selective conductive plug on the selective silicon layer.

Abstract: A method for fabricating a field oxide layer capable of being applied to highly integrated circuits. The semiconductor device according to the present invention prevents electric field concentration at the corners of the active region, by filling a recess generated in a field oxide layer with an additional oxide spacer. The method includes the steps of a) forming a trench in a semiconductor substrate; b) forming an insulating layer on the resulting structure and burying the trench; c) forming a field oxide layer by controlling topology of the insulating layer in a wet etching process, wherein the wet etching process forms a recess at a corner of the field oxide layer so that a portion of sidewalls of the active region is exposed; d) forming an additional field oxide spacer layer at the recess in order to bury the exposed sidewall portion of the active region; and e) vertically growing an epitaxial layer on the exposed active region.

Abstract: An epi-channel of a uniform shape is formed by adjusting the temperature and pressure of H2 bake process to prevent the etching of a separation oxide at an interface of an active region and a field region thereby ensuring that an epi-channel is formed having a uniform shape.

Abstract: Disclosed is a method for fabricating a MOSFET device (and the MOSFET device itself) having a metal gate capable of forming an ultra shallow junction and allowing application of a self-aligned contact as a following process.

Abstract: An epi-channel of a uniform shape is formed by adjusting the temperature and pressure of H2 bake process to prevent the etching of a separation oxide at an interface of an active region and a field region thereby ensuring that an epi-channel is formed having a uniform shape.

Abstract: A method for fabricating a field oxide layer capable of being applied to highly integrated circuits. The semiconductor device according to the present invention prevents electric field concentration at the corners of the active region, by filling a recess generated in a field oxide layer with an additional oxide spacer. The method includes the steps of a) forming a trench in a semiconductor substrate; b) forming an insulating layer on the resulting structure and burying the trench; c) forming a field oxide layer by controlling topology of the insulating layer in a wet etching process, wherein the wet etching process forms a recess at a corner of the field oxide layer so that a portion of sidewalls of the active region is exposed; d) forming an additional field oxide spacer layer at the recess in order to bury the exposed sidewall portion of the active region; and e) vertically growing an epitaxial layer on the exposed active region.

Abstract: During selective epitaxial growth processing using LPCVD equipment, a SiGe epitaxial layer and a Si epitaxial layer are sequentially formed so that lateral overgrowth that could occur in formation of only Si epitaxial layer can be effectively restricted. By adjusting Ge density, SiGe migration is induced at selective epitaxial growth temperatures for forming the conventional Si epitaxial layer. And, by utilizing the internal stress of SiGe and lattice mismatch between the SiGe epitaxial layer and the Si epitaxial layer, the lateral overgrowth is restricted. Furthermore, by hydrogen thermal processing, surface topology of the epitaxial layer is improved.

Abstract: A method of manufacturing a semiconductor device having the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a selective silicon layer in the contact hole, and forming a selective conductive plug on the selective silicon layer.